1 / 18

Task 8 - HADES1 Resistive Plate Chamber (RPC) Time of Flight Wall P.Fonte LIP-Coimbra

“DIRAC-PHASE-1” – Construction stage 1 at the international Facility for Antiproton and Ion Research (FAIR) at GSI, Darmstadt. 2 nd Annual Report meeting GSI, 11-10-2007. Task 8 - HADES1 Resistive Plate Chamber (RPC) Time of Flight Wall P.Fonte LIP-Coimbra.

denzel
Download Presentation

Task 8 - HADES1 Resistive Plate Chamber (RPC) Time of Flight Wall P.Fonte LIP-Coimbra

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. “DIRAC-PHASE-1” – Construction stage 1 at the international Facility for Antiproton and Ion Research (FAIR) at GSI, Darmstadt 2nd Annual Report meeting GSI, 11-10-2007 Task 8 - HADES1 Resistive Plate Chamber (RPC) Time of Flight Wall P.FonteLIP-Coimbra Construction of a high-granularity and large area time of flight wall for the HADES spectrometer based on Resistive Plate Counters technology. Production of fast, wide-band, analog electronic and multi-hit digital electronic with the aim to achieve time resolution better than 100 ps and feasible to run in a high multiplicity environment of heavy ion collisions.

  2. Participants & Tasks Along with an important contribution of CSIC, Valencia: A.Gil.

  3. Today 2006 2007 2008 Workplan status 2 full chambers produced 6 full chambers produced FEE design freeze-out  Read-out board design freeze-out  Beamtime next week Full system test

  4. Detectors (prototype sextant) LIP

  5. Detectors (prototype sextant) LIP

  6. Detectors (prototype sextant) LIP Crosstalk on the1-2 mV/V level at 300MHz

  7. Detectors (prototype sextant) LIP

  8. Detectors (prototype sextant) LIP

  9. R Discriminator Step Σ4ch. Trigger Out. Amplifier Step MAX9601-2ch 500ps Propagation Delay 2k2 In Q Q/ BFT92 Wideband PNP Transistor C C Latch enable/ 4 ch. out BGM1013 (35dB, 2GHz) PECL- LVDS ToF-Threshold C 2nd integration RC=20ns SN65LVDS100 OPA690 Wideband Op. Amplifier R ToT Integrator Task: FEE design USC, GSI, U.Valencia: ESTRELA FEE • Motherboard (MB) + Daughterboard (DB) philosophy. • DB Step5 (4 channels): 1) Amplifier stage → Ph-BGM1013 + Q-ToT stage with TI OPA690. 2) Discriminator stage: - Dual MAX 9601 discriminator. One discriminator/channel. - PECL-LVDS TI SN65LVDS100 converter. - BFT92 transistor for multiplicity trigger sum. 3) Output: 40-pin SAMTEC HSEC8 connector • MB (32 channels) by CSIC Valencia : - Provides regulated Voltage, DAC thresholds, test pulses, output path to DAQ… Frozen in February 2007

  10. Task: FEE prototype USC, GSI, U.Valencia: ESTRELA FEE Daugtherboards Motherboards provided (+ power supplies) by CSIC,Valencia(not in this project)

  11. Task: FEE prototype USC, GSI, U.Valencia: ESTRELA FEE

  12. Task: FEE prototype status USC, GSI, U.Valencia: ESTRELA FEE

  13. Task: Software USC Slow control - Thresholds DACs controlled individually, from a PC, via SPI protocol - Measurement of the temperatures sensors at the TRB is ready - Slow control to be implemented in EPICS not ready Detector software Almost all the decoding and calibration basic programs are already written and implemented in the HADES standard analysis framework Hydra. - Lookup table: sector/column/cell/side <-> DAQ channels and FEE address - Decoding/Calibration chain from raw data to hit level (including diagnostic and monitoring histograms) - Programs correlating RPC hits with MDCs and Shower hits for efficiencies analysis - Macros for the analysis of time and position resolution and FEE performances - Simulation of C-Be collisions at the hit level in order to compare the results with the expected distributions.

  14. Task: Readout board production JU, GSI • TRB Features: • ➢Four HPTDC each 32 channels => 128 channels • ➢ Single chip computer with 100MBit/s Ethernet • ➢ FPGA as board controller • ➢ DC/DC 48V • ➢ Buffer Memory • Status: In production • ➢ The board was fully integrated with HADES DAQ environment • ➢ Was used for readout in Nov 2005, May 2006 and April-May 2007 beam times • ➢ It is running stably with up to 80kHz LVL1 (for small events) and 20 kHz LVL2 rate, • ➢ data rate to 1.2 MB/s 12/24 units have been produced

  15. Major difficulties (mechanics) Mechanical drawing Needed to learn new CAD tool  perfect prototype HV distribution Full redesign: epoxy isolation (unreliable)  seamless acrylic box

  16. Major difficulties (electronics) Design GHz-bandwidth dense mixed-signal circuit – not easy (frozen February 2007) Production Component ordering difficulties Loading went not so well – lots of rework needed HADES April-May beam time got on the way

  17. M3: Full system prototype Full-system prototype 400 time+charge channels Beamtime next week

  18. SIS shutdown 2009 M40 M32 M33 M34 M35 M36 M37 M39 M38 M43 M44 M45 M46 M47 M48 M42 M41     Workplan update

More Related