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Single-Cycle Instructions

Single-Cycle Instructions. VHDL Tutorial R. E. Haskell and D. M. Hanna T5: VHDL ROM. T5: Instruction ROM. Tcount.vhd. -- A 4-bit up-counter library IEEE; use IEEE.std_logic_1164. all ; use IEEE.std_logic_unsigned. all ; entity Tcount is port ( clr: in STD_LOGIC;

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Single-Cycle Instructions

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  1. Single-Cycle Instructions VHDL Tutorial R. E. Haskell and D. M. Hanna T5: VHDL ROM

  2. T5: Instruction ROM

  3. Tcount.vhd -- A 4-bit up-counter library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity Tcount is port ( clr: in STD_LOGIC; clk: in STD_LOGIC; q: out STD_LOGIC_VECTOR (3 downto 0) ); end Tcount;

  4. Tcount.vhd architecture Tcount_arch of Tcount is begin process (clk, clr) variable COUNT: STD_LOGIC_VECTOR (3 downto 0); begin if clr = '1' then q <= "0000"; elsif clk'event and clk='1' then COUNT := COUNT + 1; q <= COUNT; end if; end process; end Tcount_arch;

  5. Trom.vhd library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity Trom is port ( addr: in STD_LOGIC_VECTOR (3 downto 0); M: out STD_LOGIC_VECTOR (4 downto 0) ); end Trom;

  6. Trom.vhd architecture Trom_arch of Trom is constant SWpush: STD_LOGIC_VECTOR (4 downto 0) := "11000"; constant plus: STD_LOGIC_VECTOR (4 downto 0) := "01100"; constant oneplus: STD_LOGIC_VECTOR (4 downto 0) := "01101"; constant invert: STD_LOGIC_VECTOR (4 downto 0) := "01110"; constant twotimes: STD_LOGIC_VECTOR (4 downto 0) := "01111"; constant dup: STD_LOGIC_VECTOR (4 downto 0) := "10000";

  7. Trom.vhd subtype rom_word is std_logic_vector(4 downto 0); type rom_array is array (0 to 7) of rom_word); constant rom: rom_array := ( SWpush, SWpush, plus, twotimes, DUP, invert, oneplus, plus );

  8. Trom.vhd begin process(addr) variable j: integer; begin j := conv_integer(addr); M <= rom(j); end process; end Trom_arch;

  9. T5main.vhd library IEEE; use IEEE.std_logic_1164.all; entity T5main is port ( SW: in STD_LOGIC_VECTOR (1 to 8); BTN: in STD_LOGIC_VECTOR (1 to 4); LD: out STD_LOGIC_VECTOR (1 to 8); AtoG: out STD_LOGIC_VECTOR (6 downto 0); A: out STD_LOGIC_VECTOR (3 downto 0) ); end T5main;

  10. architecture T5main_arch of T5main is signal tin, T, N, y: std_logic_vector(7 downto 0); signal P: std_logic_vector(3 downto 0); signal M: std_logic_vector(4 downto 0); signal clr, clk: std_logic; begin U0: mux2 port map (a =>SW, b => y, sel => M(2), y => tin); Treg: reg port map (d => tin, load =>M(3), clr => clr, clk =>clk, q => T); Nreg: reg port map (d => T, load => M(4), clr => clr, clk =>clk, q => N); U1: alu port map (a => T, b => N, sel => M(1 downto 0), y => y); U2: step_display port map (dig1 => T(3 downto 0), dig2 => T(7 downto 4), dig3 => N(3 downto 0), dig4 => N(7 downto 4), step => BTN(4), clr => BTN(1), clkout => clk, clrout => clr, A => A, AtoG => AtoG); U3: Tcount port map (clr => clr, clk => clk, q => P); U4: Trom port map (addr => P, M => M); LD <= SW; end T5main_arch;

  11. Lab Exercise T5

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