1 / 79

Digital Electronics 2 EET 202

Digital Electronics 2 EET 202. CHAPTER 2 : SHIFT REGISTER Ahmad Zaidi Bin Abdullah E-mel : azba5@yahoo.com. Learning Outcomes. After learning this chapter, students should be able to; Identify the basic forms of data movement in shift registers.

diannerusso
Download Presentation

Digital Electronics 2 EET 202

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Digital Electronics 2EET 202 CHAPTER 2 : SHIFT REGISTER Ahmad Zaidi Bin Abdullah E-mel : azba5@yahoo.com EET 202- Digital Electronics 2

  2. Learning Outcomes After learning this chapter, students should be able to; • Identify the basic forms of data movement in shift registers. • Explain how serial in/serial out (SISO), serial in/parallel out (SIPO), parallel in/serial out (PISO) and parallel in/parallel out (PIPO) shift register operate. • Determine how bidirectional shift register operates. • Analyze output waveform for general shift register • Construct Johnson and ring counters from shift register • Describe shift register applications such as time delay, serial to parallel converter, universal asynchronous receiver transmitter (UART) and keyboard encoder. EET 202- Digital Electronics 2

  3. Chapter Cover • Basic shift register functions • SISO - shift registers • SIPO - shift registers • PISO - shift registers • PIPO - shift registers • Bidirectional shift registers • Shift register counters • Shift register applications EET 202- Digital Electronics 2

  4. Introduction • Register – one or more flip-flops used to store or hold data • A group of flip-flops used to shift/transfer data from flip-flop to flip-flop. • A group of D flip-flops connected in a chain and the clock of the flip-flops is connected in a synchronous manner. • They are generally provided with a Clear or Reset connection so that they can be "SET" or "RESET" as required. • Shift registers are available in IC form or can be constructed from discrete flip-flop

  5. Sequential Logic Circuits Combinational outputs Memory outputs Combinational logic Memory elements Inputs Sequential circuit = Combinational logic + Memory Elements Current State of A sequential Circuit: Value stored in memory elements (value of state variables). State transition: A change in the stored values in memory elements thus changing the sequential circuit from one state to another state.

  6. 74LS175 CLK CLR 1D 1Q 1Q 2D 2Q 2Q 3D 3Q 3Q 4D 4Q 4Q An n-bit register is a collection of n D flip-flops with a common clock used to store n related bits. Example: 74LS175 4-bit register

  7. Shift Registers Socketed 74LS164 8-Bit ShiftRegisterChip EET-202 Digital Electronics 2

  8. Shift Registers • A shift register is a register in which the contents may be shifted one or more places to the left or right. This type of register is capable of performing a variety of functions. It may be used for serial-to-parallel conversion and for scaling binary numbers.

  9. Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0 RSI 0 1 1 1 0 1 1 1 LSI Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0 RSI 0 1 1 1 1 1 LSI Shift Registers • Multi-bit register that moves stored data bits left/right ( 1 bit position per clock cycle) • Shift Left is towards MSB • Shift Right (or Shift Up) is towards LSB

  10. Shift Registers Characteristics • It is a temporary memory and holds the numbers on display. • Consist of an arrangement of flip-flops • Important in applications involving storage and transfer of data (data movement) in digital system • Used for storing and shifting data (1s and 0s) entered into it from an external source and possesses no characteristic internal sequence of states. • D flip-flops are use to store and move data • It shifts the number to the to the left on the display each time a new digit is pressed on the keyboard.

  11. Example: • Calculator Example: • Press & release 1 on keyboard & 1 displayed right. • Press & release 1 on keyboard & 1 displayed right, 11 displayed. • Press & release 3 on keyboard & 3 displayed right, 113 displayed

  12. D D D D Q Q Q Q CLK CLK CLK CLK FF A FF A FF A FF A CLR CLR CLR CLR Digital System Using Shift Registers Output Display Input Keyboard Encoder Shift Register Processing Unit Shift Register Decoder 7 8 9 4 5 6 1 2 3 0 • 4-bit serial load shift register A B C D Data Input Clock Clear

  13. Storage Register Group of storage elements read/written as a unit 4-bit register constructed from 4 D FFs Shared clock and clear lines Schematic Shape TTL 74171 Quad D-type FF with Clear

  14. The flip-flop as a storage element • The storage capacity is the total number of bits of digital data it can retain. The total number of bits depend on the number of flip-flops being used. • Storage capability make it important type of memory devices Still remember the truth table for D flip flop?

  15. When a 1 is on D, Q becomes a 1 at triggering edge of CLK or remains a 1 if already in the SET state When a 0 is on D, Q becomes a 0 at triggering edge of CLK or remains a 0 if already in the RESET state

  16. (Four bits are used for illustration. The bits move in the direction of the arrows.) data movement in shift register

  17. Shift Register Classifications • Where bits come in & go out: • Serial in-serial out (SISO) • Serial in-serial out (SIPO) • Parallel in serial out (PISO) • Parallel in-parallel out( PIPO) MSB LSB MSB LSB

  18. Serial & Parallel Transfers & Conversion • SERIAL TRANSFER means that the data is moved along a single line one bit at a time. A control pulse is required to move each bit. • PARALLEL TRANSFER means that each bit of data is moved on its own line and that all bits transfer simultaneously as they did in the parallel register. A single control pulse is required to move all bits.

  19. SERIN D Q CLK CLOCK D Q CLK · SRG n · > · SI SO SEROUT D Q CLK Serial In, Serial Out Shift Register(SISO) For a n-bit SRG: Serial Out = Serial In delayed by n clock period 4-bit shift register example: Serial in: 1 0 1 1 0 0 1 1 1 0 Serial out: - - - - 1 0 1 1 0 0 clock:

  20. SISo • The serial in/serial out shift register accepts data serially – that is, one bit at a time on a single line • It produces the stored information on its output also in serial form. • Example of IC: 74HC165, 74HC195 • Each clock pulse will move an input bit to the next flip-flop. Figure 1 shows 5- bit SISO shift register

  21. SISO

  22. SISO- Timing diagram

  23. SISO- 12bit

  24. Try To shift 101 starting with LSB Draw timing diagram for 6 clk pulse

  25. SERIAL IN PARALLEL OUT SHIFT REGISTER (SIPO) • Data bits are entered serially (LSB first) in a SIPO shift register in the same manner as SISO. Example of IC: 74HC164, 74HC195 • The difference is the way in which the data bits are taken out of the register; in the parallel output register. • Data bits are taken out in parallel • Once all bits are store, the bits are shifted out simultaneously CENT-113 Digital Electronics

  26. SRG n > SERIN 1Q D Q CLK SI 1Q CLOCK 2Q · · · 2Q D Q CLK nQ · · · nQ D Q CLK SERIAL IN PARALLEL OUT SHIFT REGISTER (SIPO) (PO) Serial to Parallel Converter Example: 4-bit shift register serin: 1 0 1 1 0 0 1 1 1 0 1Q: - 1 0 1 1 0 0 1 1 1 2Q: - - 1 0 1 1 0 0 1 1 3Q: - - - 1 0 1 1 0 0 1 4Q: - - - - 1 0 1 1 0 0 clock:

  27. SERIN D Q CLK SERIN 1Q D Q CLK CLOCK CLOCK D Q CLK 2Q D Q CLK · · · · · · SEROUT D Q CLK nQ D Q CLK Can u see the difference?

  28. Eg: binary no. 1011 is loaded sequentially, one bit at each clock pulse SIPO EXAMPLE 1

  29. Eg: binary no. 0110 is entered.Register initially contain all 1. SIPO EXAMPLE 1

  30. Are u okay? • Let take some refreshment… • Link to Video SIPO • Let’s see some animation

  31. PARALLEL IN SERIAL OUT SHIFT REGISTER (PISO)

  32. PISO – Shift Register • Data bits are entered parallel on the same time and data bits are shifted out in a single line. Example of IC: 74HC165, 74HC195 • D0, D1, D2 and D3 are parallel inputs where, D0 is MSB and D3 is LSB. • To write data in, the mode control line is taken to LOW and the data is clocked in. The data can be shifted when the mode control line is HIGH as SHIFT is active high

  33. 4 BIT PISO • When signal = 1, • SHIFT When signal = 0,  LOAD

  34. 4 BIT PISO • When signal = 0, • LOAD G1 – G3 enabled

  35. 4 BIT PISO • When signal = 1, • SHIFT G4 – G6 enabled

  36. 4 BIT PISO

  37. Can you try and trace the output for each FF stage until you get Q3?

  38. EXAMPLE 1 0 1 0 Assume that the signal has values 011011 for 6 respective clock cycle For the parallel data input Assume D0 = 1, D1 = 0, D2 = 1, D3 = 0

  39. 0 1 1 1 0 0 0 CLK 1, Signal = 0 G1 – G3 Will get value = 1 G4 – G6 Will get value = 0 Referring to the AND gate theory, All gates that receives “0” values at shift/load can be ignored.

  40. 1 1 0 1 1 1 0 Now, AND the shift/load with respective Data bit, D0 – D3

  41. 1 0 0 0 1 1 1 CLK 2, Signal = 1 G1 – G3 Will get value = 0 G4 – G6 Will get value = 1 Referring to the AND gate theory, All gates that receives “0” values at shift/load can be ignored.

  42. 1 1 1 1 0 1 0 Now, AND the shift/load value with Respective data that goes into G4, G5, G6

  43. How do you put it in table? For the parallel data input Assume D0 = 1, D1 = 0, D2 = 1, D3 = 0

  44. PISO

  45. Parallel in - Parallel out Register • We have now added logic to allow current data to be retained (by feedback from flip flop output) or new data to be loaded from external inputs. • Control mode of operation via “Load” switch: • Load = 1 means load new data; • Load = 0 means retain existing data. • Clock now runs freely without skew or switching. • i.e. 74195.

  46. PARALLEL IN PARALLEL OUT SHIFT REGISTER (PIPO) • Immediately following simultaneous entry of all data bits, it appear on parallel output.

  47. PIPO

  48. PIPO….

More Related