LSI Logic Japan Semiconductor

1. LSI Logic Japan Semiconductor Manufacturing Process

2. Si wafer What part at LLJS ? LSI Logic Japan Semiconductor LSI Logic Japan Patterned wafer Sorted wafer Customer Assembly

3. Poly Si Gate Gate Oxide N-MOS Tr. P-MOS Tr. Field Oxide Field Oxide N+ S/D P+ S/D P-Well Silicon N-Well LSI Logic Japan Semiconductor CMOS Cross Section

4. LSI Logic Japan Semiconductor CMOS 3LM Cross Section W Plug Meatl-3 Metal-2 Insulator Metal-1 Silicon

5. LSI Logic Japan Semiconductor Cross Section of Process Flow - Field Oxidation - Si3N4 SiO2 Pad P-Sub. Oxidation SiO2 Bird’s beak P-Sub.

6. LSI Logic Japan Semiconductor Cross Section of Process Flow - Implantation, Diffusion - Impla Resist SiO2 P-Sub. Diff (Anneal at ~900℃） Well P-Sub.

7. Diffusion Ion Implant Cleaning Masking Etching CVD Process Cycle LSI Logic Japan Semiconductor CMP PVD

8. Masking Process - Stepper Optics - LSI Logic Japan Semiconductor Fly’s Eye Lens Mask Elliptic Mirror Mercury Arc Lamp Projection Lens Photo Resist Si Wafer

9. LSI Logic Japan Semiconductor Masking Process - Development - Exposure Developer Resist Sub. Sub. Etching Sub.

10. LSI Logic Japan Semiconductor Masking Process - Projected Image -

11. LSI Logic Japan Semiconductor Cleaning Process - RCA Wet Station - DIW Filter Filter P P HF bath Oxide Strip OR bath DI water Rinse SC-1 bath Organic Remove QDR bath DI water Rinse Cooling tube DIW Filter P IPA vapor bath Drying FR bath DI water Rinse H-QDR bath Hot DI water Rinse SC-2 bath Metal Remove

12. Oxidation Process - Vertical Furnace - LSI Logic Japan Semiconductor Quartz Boat Wafer Quartz Tube Heater TC Exhaust Lamp Silicon chip H2, N2 O2, N2, HCl

13. Accelerator Y-Scanning Plate Analyzer Magnet Wafer Ion Beam Slit X-Scanning Plate Disk Gas Source Ion Source Power Supply LSI Logic Japan Semiconductor Ion Implatation Process

14. Heater Outer Tube Boat Wafer Inner Tube Quartz Cap Vacuum Reactive Gas LP-CVD Process ( Hot Wall Type Vertical Furnace ) LSI Logic Japan Semiconductor

15. #2 #1 #3 Loadlock Chamber Reactor Chamber #4 #5 #7 #6 LSI Logic Japan Semiconductor PE-CVD Process (Dual Frequency, Multi-station Sequential Deposition)

16. AP-CVD Process (Wafer Face Down, Multi-D/H Sequential Deposition) LSI Logic Japan Semiconductor

17. PVD Process - DC Magnetron Sputtering - LSI Logic Japan Semiconductor Plasma Area Magnet Target Al or Ti Ar+ Shield Ar+ Power Supply Wafer + Vacuum Pump Ar Gas

18. RF POWER Etching Process LSI Logic Japan Semiconductor Process chamber GAS [ CF4, CHF3 , Cl2 ] ANODE WAFER CATHODE VACUUM PUMP

19. LSI Logic Japan Semiconductor CMP (Chemical Mechanical Polishing) Process Principle Slurry Force Wafer Carrier Polishing Pad Wafer Table The surface of the wafer is polished by the slurry.

20. In-Line Monitoring Tools LSI Logic Japan Semiconductor

21. In-Line Monitoring Flow 1 LSI Logic Japan Semiconductor Defect Map Trend Chart Wafer Inspection Microscope SEM Defect Classification

22. In-Line Monitoring Flow 2 LSI Logic Japan Semiconductor Elemental Analysis (EDX) Analysis & Investigation Cross-Section (FIB) Feedback to Root Cause Electron Mode Ion Mode

23. LSI Logic Japan Semiconductor Process Trend Lithography : KrF, ArF, F2, EUV Metallization : Cu, Low-K Manufacturing : 300mm, Single Wafer

24. LSI Logic Japan Semiconductor Semiconductor Business 226.5 B$ ~ World / yr 2000 2.7 B$ ~ LSI / yr 2000