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Lecture 4-2 ARM Interrupt

Lecture 4-2 ARM Interrupt. ARM Interrupt Next Lecture DMA Buses Standard I/O Interface. Processor Modes. The ARM has seven basic operating modes: User : unprivileged mode under which most tasks run FIQ : entered when a high priority (fast) interrupt is raised

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Lecture 4-2 ARM Interrupt

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  1. Lecture 4-2ARM Interrupt • ARM Interrupt • Next Lecture • DMA • Buses • Standard I/O Interface

  2. Processor Modes • The ARM has seven basic operating modes: • User : unprivileged mode under which most tasks run • FIQ : entered when a high priority (fast) interrupt is raised • IRQ : entered when a low priority (normal) interrupt is raised • Supervisor : entered on reset and when a Software Interrupt instruction is executed • Abort : used to handle memory access violations • Undef : used to handle undefined instructions • System : privileged mode using the same registers as user mode

  3. ARM Interrupt Structure - Exceptions • There are five sources for exceptions • Two are external request lines • IRQ and FIQ (Fast Interrupt Request) • One software interrupt (SWI)  Supervisor mode • Two exceptions that may be caused by abnormal conditions during program execution • Abort by bus error and Undefined instruction • Exceptions are handled according to the following priority • Reset (highest priority) • Data abort • FIQ • IRQ • Prefetch abort • Undefined instruction (lowest priority) • Reset overrides all other conditions to bring the processor to a known starting condition

  4. The ARM Register Set Current Visible Registers Current Visible Registers Current Visible Registers Current Visible Registers Current Visible Registers Current Visible Registers r0 r0 r0 r0 r0 r0 r0 Abort Mode SVC Mode Undef Mode FIQ Mode User Mode IRQ Mode r1 r1 r1 r1 r1 r1 r1 r2 r2 r2 r2 r2 r2 r2 Banked out Registers Banked out Registers Banked out Registers Banked out Registers Banked out Registers Banked out Registers r3 r3 r3 r3 r3 r3 r3 r4 r4 r4 r4 r4 r4 r4 r5 r5 r5 r5 r5 r5 r5 User User User User User FIQ FIQ FIQ FIQ FIQ FIQ IRQ IRQ IRQ IRQ IRQ IRQ SVC SVC SVC SVC SVC SVC Undef Undef Undef Undef Undef Undef Abort Abort Abort Abort Abort Abort r6 r6 r6 r6 r6 r6 r6 r7 r7 r7 r7 r7 r7 r7 r8 r8 r8 r8 r8 r8 r8 r8 r8 r8 r8 r8 r8 r8 r9 r9 r9 r9 r9 r9 r9 r9 r9 r9 r9 r9 r9 r9 r10 r10 r10 r10 r10 r10 r10 r10 r10 r10 r10 r10 r10 r10 r11 r11 r11 r11 r11 r11 r11 r11 r11 r11 r11 r11 r11 r11 r12 r12 r12 r12 r12 r12 r12 r12 r12 r12 r12 r12 r12 r12 r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r15 (pc) r15 (pc) r15 (pc) r15 (pc) r15 (pc) r15 (pc) r15 (pc) cpsr cpsr cpsr cpsr cpsr cpsr cpsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr

  5. Register Organization Summary r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 (sp) r14 (lr) r15 (pc) cpsr User FIQ IRQ SVC Undef Abort Usermoder0-r7,r15,andcpsr Usermoder0-r12,r15,andcpsr Usermoder0-r12,r15,andcpsr Usermoder0-r12,r15,andcpsr Usermoder0-r12,r15,andcpsr Thumb state Low registers r8 r9 Thumb state High registers r10 r11 r12 r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) spsr spsr spsr spsr spsr Note: System mode uses the User mode register set

  6. Condition code flags N = Negative result from ALU Z = Zero result from ALU C = ALU operation Carried out V = ALU operation oVerflowed Sticky Overflow flag - Q flag Architecture 5TE/J only Indicates if saturation has occurred J bit Architecture 5TEJ only J = 1: Processor in Jazelle state Interrupt Disable bits. I = 1: Disables the IRQ. F = 1: Disables the FIQ. T Bit Architecture xT only T = 0: Processor in ARM state T = 1: Processor in Thumb state Mode bits Specify the processor mode Program Status Registers 31 28 27 24 23 16 15 8 7 6 5 4 0 N Z C V Q I F T mode U n d e f i n e d J f s x c

  7. 7 6 5 4 3 2 1 0 I F M4 M3 M2 M1 M0 ARM Program Status Register • Lower order bits of the CPSR (current program status register) • There are two interrupt mask bits, one each for IRQ and FIQ • When either bits is equal to 1, the corresponding interrupt is disabled • The register also contains five mode bits M0-M4, they indicate in which mode the processor is running • There is a user mode and five privileged modes, one for each of the five types of exception • When the processor switches to a different mode, it also switches some of the registers accessible to the program • Example, Register R0 to R7, R15 (PC) and CPSR are accessible in all modes

  8. Exception Handling 0x1C 0x18 0x14 0x10 0x0C 0x08 0x04 0x00 • When an exception occurs, the ARM: • Copies CPSR into SPSR_<mode> • Sets appropriate CPSR bits • Change to ARM state • Change to exception mode • Disable interrupts (if appropriate) • Stores the return address in LR_<mode> • Sets PC to vector address • To return, exception handler needs to: • Restore CPSR from SPSR_<mode> • Restore PC from LR_<mode> This can only be done in ARM state. FIQ IRQ (Reserved) Data Abort Prefetch Abort Software Interrupt Undefined Instruction Reset Vector Table Vector table can be at 0xFFFF0000 on ARM720T and on ARM9/10 family devices

  9. Software Interrupt (SWI) 0 • Causes an exception trap to the SWI hardware vector • The SWI handler can examine the SWI number to decide what operation has been requested. • By using the SWI mechanism, an operating system can implement a set of privileged operations which applications running in user mode can request. • Syntax: • SWI{<cond>} <SWI number> 31 28 27 24 23 Cond 1 1 1 1 SWI number (ignored by processor) Condition Field

  10. Actions in Response to Exception • It saves the return address in R14 of the corresponding mode • It saves CPSR into the corresponding SPSR • It changes the mode bits in CPSR for the type of interrupt. For FIQ and IRQ it also sets the corresponding mask bit in CPSR to 1, thus disabling further interrupts. • It branches to the interrupt service routine • The ARM processor uses pipelining  an instruction is fetched before the execution of the previous instruction is completed • Let I1 be at address A, when I1 is being executed the PC is incremented to point to I2 (prefetched instruction for pipelining). The PC is incremented again to point to I3. Assume that the an interrupt occurs while executing I1  the content of the PC= A+8 which is one address higher than the normal return address, A+4.

  11. Actions in Response to Exception • The interrupt service routine must subtract 4 from R14 before using its content as the return address • e.g. SUBS PC, R14_irq, #4 • The S means set condition codes, however when the target register is the PC, the suffix S causes the processor to copy the content of SPSR_irq into CPSR, this completes the actions required by a return from interrupt. • The amount subtracted from R14 depends on the details of instruction execution in the processor pipeline  it depends on the type of instruction being executed • For example in the case of a software interrupt, the value saved in R14_svc is the correct return address • The return from SWI can be accomplished by the following instruction : MOVS PC, R14_svc

  12. Address Correction During INT Return Exception saved address return address return instruction Undefined inst. PC+4 PC+4 MOVS PC, R14_und Software Inter. PC+4 PC+4 MOVS PC, R14_svc Prefetch abort PC+4 PC SUBS PC, R14_abt, #4 Data abort PC+8 PC SUBS PC, R14_abt, #8 IRQ PC+4 PC SUBS PC, R14_irq, #4 FIQ PC+4 PC SUBS PC, R14_fiq, #4 • When running in privileged mode two special MOV instructions transfer data to or from either the current or saved PSR MRS R0, CPSR copies the content of CPSR into R0 MSR SPSR, R0 copies the content of R0 into SPSR • These instructions are useful when the OS needs to enable or disable interrupts

  13. Interrupt Nesting and Stack • The ARM interrupt mechanism stores the return address in a register (R14) • Nesting is possible when caused by different sources: e.g. the IRQ interrupt service routine (return address stored in R14_irq) can be interrupted by the higher priority FIQ interrupt (return address in R14_fiq) • Nesting of interrupts from the same source • The contents of R14 and SPSR must be saved on the stack • Can be done using R13 as the stack pointer •  this is why R13 and R14 are available in all the modes • The interrupt service routine can save R14 and SPSR on its private stack, then clear the interrupt mask in CPSR

  14. Interrupt Nesting and Stack • In order to save other registers and restore them, the following instructions can be used • STMFD R13!, {R0,R1,R2,R14} • LDMFD R13!, {R0,R1,R2,R15}^ • ^  causes the processor to copy SPSR into CSPR at the same time it loads R15 • In the case of a software interrupt or instruction prefetch exception, the value restored to R15 is also the correct return address • LDM cannot be used to return from an IRQ or FIQ interrupt because the content of saved R14 must be corrected first.

  15. Example • Reading a line of characters from the keyboard • The keyboard is connected to the interrupt line IRQ • The corresponding interrupt vector location contains a branch to READ • By the time this code segment is entered, the memory buffer, LINE, has been loaded into location PNTR • Locations of PNTR and EOL are sufficiently close in the address space that they can be reached with the relative addressing mode

  16. Example • The main program enables interrupts in both the keyboard interface and the processor by setting • The KEN flag in the Keyboard’s CONTROL register and • Clearing the I mask in the processor status register (the I mask, bit 7, is cleared by loading $50 into CPSR) • The LDM and STM are used to save and restore registers • The SUBS is used to return to the interrupted program • The address of the keyboard’s DATAIN register is loaded in a processor register using the ADR instruction • The address of the CONTROL register is equal to DATAIN+3

  17. Example: Main Program MOV R0,#0 STR R0,EOL Clear EOL flag ADR R1, DATAIN Load address of register DATAIN LDRB R0, [R1,#3] Get contents of CONTROL register ORR R0, R0,#4 Set bit KEN in the CONTROL register STRB R0, [R1,#3] to enable keyboard interrupts MOV R0, #&50 Enable IRQ interrupts in processor MSR CPSR, R0 and switch to user mode ….

  18. Example: ISR READ STMFD R13!,{R0-R2,R14_irq} Save R0,R1, R2 and R14_irq on the stack ADR R1, DATAIN Load address of register DATAIN LDRB R0, [R1] Get input character LDR R2, PNTR Load pointer value STRB R0,[R2],#1 Store character and increment pointer STR R2, PNTR Update pointer value in memory CMPB R0,#&0D Check if carriage return LDMNEFD R13!,{R0-R2,R14_irq} if not restore registers SUBNES PC, R14_irq,#4 and return LDRB R0,[R1,#3] otherwise, get CONTROL register AND R0,R0,#&FB clear bit KEN STRB R0, [R1,#3] to disable keyboard interrupts MOV R0,#1 set EOL flag STR R0, EOL LDMFD R13!,{R0-R2,R14_irq} Restore registers SUBS PC, R14_irq, #4 and return

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