1 / 128

EENG 2710 Chapter 4

EENG 2710 Chapter 4. Modular Combinational Logic. Chapter 4 Homework. EENG 2710 Xilinx Project 1 And EENG 2710 VHDL Project 2 (Projects are on Instructor’s Website). Basic Decoder. Decoder: A digital circuit designed to detect the presence of a particular digital state.

enrico
Download Presentation

EENG 2710 Chapter 4

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. EENG 2710 Chapter 4 Modular Combinational Logic

  2. Chapter 4 Homework EENG 2710 Xilinx Project 1 And EENG 2710 VHDL Project 2 (Projects are on Instructor’s Website)

  3. Basic Decoder • Decoder: A digital circuit designed to detect the presence of a particular digital state. • Can have one output or multiple outputs. • Example: 2-Input NAND Gate detects the presence of ‘11’ on the inputs to generate a ‘0’ output.

  4. Single-Gate Decoders • Uses single gates (AND/NAND) and some Inverters. • Example: 4-Input AND detects ‘1111’ on the inputs to generate a ‘1’ output. • Inputs are labeled D3, D2, D1, and D0, with D3 the MSB (most significant bit) and D0 the LSB (least significant bit).

  5. Single-Gate Decoders D3 D3 D2 D2 D1 D1 D0 D0 Y = (D3 D2 D1 D0)’ Y = D3 D2 D1 D0

  6. Single-Gate Examples • If the inputs to a 4-Input NAND are given as , then the NAND detects the code 0001. The output is a 0 when the code 0001 is detected. • This type of decoder is used in Address Decoding for a PC System Board.

  7. Multiple Output Decoders • Decoder circuit with n inputs can activate m = 2n load circuits. • Called a n-line-to-m-line decoder, such as a 2-to-4 or a 3-to-8 decoder. • Usually has an active low enable that enables the decoder outputs.

  8. 2-to-4 Decoder

  9. 3-to-8 Decoder

  10. Truth Table for a 3-to-8 Decoder

  11. 74138 3-to-8 Decoder

  12. 74138 3-to-8 Decoder

  13. Simulation • Simulation: The verification of a digital design using a timing diagram before programming the design in a Complex Programmable Logic Device (CPLD). • Used to check the Output Response of a design to an Input Stimulus using a timing diagram.

  14. Simulation

  15. VHDL Binary Decoder • Use select signal assignment statements constructs or conditional signal assignment statements constructs.

  16. 2-to-4 Decoder VHDL Entity • Using a select signal assignment statement: LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY decode3a IS PORT( d : IN STD_LOGIC_VECTOR (1 downto 0); g : IN STD_LOGIC y : OUT STD_LOGIC_VECTOR (3 downto 0)); END decode3;

  17. Selected Signal Entity • In the previous slide, the Entity used a STD LOGIC Array for Inputs and Outputs. • The Y : OUT STD_LOGIC_VECTOR(3 downto 0) is equal to Y3, Y2, Y1, Y0. • The STD_LOGIC Data Type is similar to BIT but has added state values such as Z, X, H, and L instead of just 0 and 1.

  18. Selected Signal Assignments • Uses a VHDL Architecture construct called WITH SELECT. • Format is: • WITH (signal input(s)) SELECT. • Signal input states are used to define the output state changes.

  19. ARCHITECTURE decoder OF decode2to4 IS SIGNAL inputs : STD_LOGIC_VECTOR (2 downto 0); BEGIN inputs(2) <= g; inputs (1 downto 0) <= d; WITH inputs SELECT y <= "0001" WHEN "000", "0010" WHEN "001", "0100" WHEN "010", "1000" WHEN "011", "0000" WHEN others; END decoder; 2-to-4 Decoder VHDL Architecture d(1) g d(0) Default case Y(3) Y(0)

  20. 2-to-4 Decoder VHDL Architecture LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY decode3a IS PORT( d : IN STD_LOGIC_VECTOR (1 downto 0); g : IN STD_LOGIC y : OUT STD_LOGIC_VECTOR (3 downto 0)); END decode3; ARCHITECTURE decoder OF decode2to4 IS SIGNAL inputs : STD_LOGIC_VECTOR (2 downto 0); BEGIN inputs(2) <= g; inputs (1 downto 0) <= d; WITH inputs SELECT y <= "0001" WHEN "000", "0010" WHEN "001", "0100" WHEN "010", "1000" WHEN "011", "0000" WHEN others; END decoder;

  21. Decoder Architecture • The decoder Architecture used a SELECT to evaluate d to determine the Output y. • Both d and y are defined as an Array (or bus or vector) Data Type. • The last state for WHEN OTHERS is added for the other logic states (Z, X, H, L, etc.).

  22. Seven-Segment Displays • Seven-Segment Display: An array of seven independently controlled LEDs shaped like an 8 that can be used to display decimal digits.

  23. Seven-Segment Displays

  24. Seven-Segment Displays

  25. Common Anode Display • Common Anode Display (CA): A seven- segment display where the anodes of all the LEDs are connected together to VCC and a ‘0’ turns on a segment (a to g).

  26. Common Cathode Display • Common Cathode Display (CC): A seven-segment display where all the cathodes are connected and tied to ground, and a ‘1’ turns on a segment.

  27. Common Cathode/Anode Display

  28. Common Anode Display

  29. Seven-Segment Decoder/Driver • Receives a BCD (Binary Coded Decimal) 4-Bit input, outputs a BCD digit 0000 – 1001 (0 through 9). • Generates Outputs (a–g) for each of the display LEDs. • Requires a current limit series resistor for each segment.

  30. Seven-Segment Decoder/Driver • Decoders for a CC-SS have active high outputs while decoders for a CA-SS have active low outputs (a to g). • The outputs generated for the binary input combinations of 1010 to 1111 are “don’t cares”. • The decoder can be designed with VHDL Logic (7447, 7448).

  31. SS Decoder/Driver Truth Table

  32. Decoder/Driver Entity (CA) ENTITY bcd_7seg IS PORT( d3, d2, d1, d0 : IN BIT; a, b, c, d, e, f, g : OUT BIT; END bcd_7seg;

  33. ARCHITECTURE seven_segment OF bcd_7seg IS SIGNAL input : BIT_VECTOR (3 downto 0); SIGNAL output : BIT_VECTOR (6 downto 0); BEGIN input <= d3 & d2 & d1 & d0; -- Uses two intermediate signals called input and output (internal no pins) -- Creates an array by using the concatenate operator (&) In this case input(3) <= d3, input(2) <= d2, etc. Decoder/Driver Architecture

  34. WITH input SELECT output <= “0000001” WHEN “0000”, “1001111” WHEN “0001”, “0010010” WHEN “0010”, “0000110“ WHEN “0011”, • • • • • • • • • “1111111” WHEN others; Decoder/Driver Architecture

  35. a <= output(6); b <= output(5); c <= output(4); d <= output(3); e <= output(2); f <= output(1); g <= output(0); END seven_segment Decoder/Driver Architecture

  36. SS VHDL File Description • In the preceding example file, a concurrent select signal assignment was used (WITH (signals) SELECT. • The intermediate output signals were mapped to the segments (a to g). • Example: when Input (D3 – D0) is 0001, the decoder sets a=d=e=f=g=1, b=c=0.

  37. Encoders • Encoder: A digital circuit that generates a specific code at its outputs in response to one or more active inputs. • It is complementary in function to a decoder. • Output codes are usually Binary or BCD.

  38. Priority Encoders • Priority Encoder: An encoder that generates a code based on the highest- priority input. • For example, if input D3 = input D5, then the output is 101, not 011. D5 has a higher priority than D3 and the output will respond accordingly.

  39. BCD Priority Encoder D9 – D0 = 0100001111 BCD # = ?

  40. BCD Priority Encoder D9 – D0 = 0101001011 Q3 – Q0 = 1000 (810)

  41. BCD Priority Encoder D9 – D0 = 1000000001 Q3 – Q0 = 1001 (910)

  42. BCD Priority Encoder D9 – D0 = 1101001011 Q3 – Q0 = 1001 (910)

  43. Put It All Together D = 1 C = 0 B = 0 A = 0 1

  44. -- hi_pri8a.vhd ENTITY hi_pri8a IS PORT( d : IN BIT_VECTOR (7 downto 0); q : OUT BIT_VECTOR (2 downto 0)); END hi_pri8a; Priority Encoder VHDL Entity

  45. ARCHITECTURE a OF hi_pri8a IS BEGIN -- Concurrent Signal Assignments q(2) <= d(7) or d(6) or d(5) or d(4); q(1) <= d(7) or d(6) or ((not d(5)) and (not d(4)) and d(3)) or ((not d(5)) and (not d(4)) and d(2)); q(0) <= -- in a similar fashion END a; Priority Encoder VHDL Architecture

  46. 8 to 3 bit Encoder

  47. 8-to-3 Encoder Truth Table

  48. Basic Multiplexers (MUX) • (MUX): A digital circuit that directs one of several inputs to a single output based on the state of several select inputs. • A MUX is called a m-to-1 MUX. • A MUX with n select inputs will require m = 2n data inputs (e.g., a 4-to-1 MUX requires 2 select inputs S1 and S0).

  49. Basic Multiplexers (MUX)

  50. Basic Multiplexers (MUX)

More Related