1 / 6

Status of TDCpix full chip assembly

Status of TDCpix full chip assembly. NA62 – GTK WG meeting. Sandro Bonacini. Full chip floorplan. Pixel matrix. 20.400x12.030 sq.mm PRELIMINARY Floorplan work started June 2012 Top assembly done in Virtuoso “South bank” P&R in Encounter Size: ~4.8 mm. “South bank”.

erno
Download Presentation

Status of TDCpix full chip assembly

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. Status of TDCpix full chip assembly NA62 – GTK WG meeting Sandro Bonacini

  2. Full chip floorplan Pixel matrix • 20.400x12.030 sq.mm • PRELIMINARY • Floorplan work started • June 2012 • Top assembly done in Virtuoso • “South bank” P&R in Encounter • Size: ~4.8 mm “South bank”

  3. South bank floorplan • Assembly of TDC, qchip, bandgaps, serializer/PLL, I/O pads & power • Pad placement is preliminary • 158 south + 4 west + 4 east • 22 staggered power pads TDC (x20) qchip (x4) config space, DLL clock & cal. fanout BGs Serializer & PLLs BG Staggered pads Staggered pads

  4. Power distribution • Regular 600-um-pitch power lines in matrix • Sparse 60-um lines in pad ring

  5. Power distribution • SW corner • I/O pads • Power/ground pads • “Pitch adapter” • Dense connections in horizontal and vertical power lines BG Staggered pads

  6. Status • Completed • Floorplan • Power planning / distribution • Next steps • “South bank” • Place & route, DFM, chip finishing • No major showstoppers • Verification (DRC, LVS) • … might need some iterations at this stage. • Complex power distribution, global nets, … • Final chip assembly

More Related