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Processor Applications

Processor Applications. General Purpose - high performance Alpha’s, SPARC, MIPS .. Used for general purpose software Heavy weight OS - UNIX, NT Workstations, PC’s Embedded processors and processor cores ARM, 486SX, Hitachi SH7000, NEC V800 Single program Lightweight, often realtime OS

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Processor Applications

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  1. Processor Applications • General Purpose - high performance • Alpha’s, SPARC, MIPS .. • Used for general purpose software • Heavy weight OS - UNIX, NT • Workstations, PC’s • Embedded processors and processor cores • ARM, 486SX, Hitachi SH7000, NEC V800 • Single program • Lightweight, often realtime OS • DSP support • Cellular phones, consumer electronics (e.g. CD players) • Microcontrollers • Extremely cost sensitive • Small word size - 8 bit common • Highest volume processors by far • Automobiles, toasters, thermostats, ... Increasing Cost Increasing volume

  2. Processor Markets $30B 32-bit micro $5.2B/17% $1.2B/4% 32 bit DSP $10B/33% DSP 16-bit micro $5.7B/19% $9.3B/31% 8-bit micro

  3. The Processor Design Space Application specific architectures for performance Embedded processors Microprocessors Performance is everything & Software rules Performance Microcontrollers Cost is everything Cost

  4. Market for DSP Products Mixed/ Signal Analog DSP DSP is the fastest growing segment of the semiconductor market

  5. Audio applications MPEG Audio Portable audio Digital cameras Wireless Cellular telephones Base station DSP Applications • Networking • Cable modems • ADSL • VDSL

  6. Another Look at DSP Applications • High-end • Wireless Base Station - TMS320C6000 • Cable modem • gateways • Mid-end • Cellular phone - TMS320C540 • Fax/ voice server • Low end • Storage products - TMS320C27 • Digital camera - TMS320C5000 • Portable phones • Wireless headsets • Consumer audio • Automobiles, toasters, thermostats, ... Increasing Cost Increasing volume

  7. DSP range of applications

  8. DSP ARCHITECTUREEnabling Technologies

  9. CELLULAR TELEPHONE SYSTEM 1 2 3 4 5 6 7 8 9 0 415-555-1212 CONTROLLER RF MODEM PHYSICAL LAYER PROCESSING BASEBAND CONVERTER A/D SPEECH ENCODE SPEECH DECODE DAC

  10. HW/SW/IC PARTITIONING MICROCONTROLLER 1 2 3 4 5 6 7 8 9 0 415-555-1212 CONTROLLER RF MODEM PHYSICAL LAYER PROCESSING BASEBAND CONVERTER ASIC A/D SPEECH ENCODE SPEECH DECODE DAC DSP ANALOG IC

  11. S/P RAM DMA DSP CORE Mapping Onto A System-on-a-chip S/P phone book keypad intfc protocol DMA control RAM µC speech quality enhancment voice recognition ASIC LOGIC RPE-LTP speech decoder de-intl & decoder Viterbi equalizer demodulator and synchronizer

  12. Example Wireless Phone Organization C540 ARM7

  13. Radio Modem Multimedia I/O Architecture Embedded Processor Sched ECC Pact Interface Low Power Bus FB Video Decomp Fifo Fifo Pen SRAM Data Flow Graphics Audio Video

  14. Graphics Out Uplink Radio Video I/O Downlink Radio Voice I/O Pen In µP Video Unit custom Coms Memory DSP Multimedia System-on-a-Chip E.g. Multimedia terminal electronics • Future chips will be a mix of processors, memory and dedicated hardware for specific algorithms and I/O

  15. Requirements of the Embedded Processors • Optimized for a single program - code often in on-chip ROM or off chip EPROM • Minimum code size (one of the motivations initially for Java) • Performance obtained by optimizing datapath • Low cost • Lowest possible area • Technology behind the leading edge • High level of integration of peripherals (reduces system cost) • Fast time to market • Compatible architectures (e.g. ARM) allows reuseable code • Customizable core • Low power if application requires portability

  16. Area of processor cores = Cost Nintendo processor Cellular phones

  17. Another figure of merit: Computation per unit area Nintendo processor Cellular phones

  18. Code size • If a majority of the chip is the program stored in ROM, then code size is a critical issue • The Piranha has 3 sized instructions - basic 2 byte, and 2 byte plus 16 or 32 bit immediate

  19. DSP BENCHMARKS - DSPstone • ZIVOJNOVIC, VERLADE, SCHLAGER: UNIVERSITY OF AACHEN • APPLICATION BENCHMARKS • ADPCM TRANSCODER - CCITT G.721 • REAL_UPDATE • COMPLEX_UPDATES • DOT_PRODUCT • MATRIX_1X3 • CONVOLUTION • FIR • FIR2DIM • HR_ONE_BIQUAD • LMS • FFT_INPUT_SCALED

  20. Evolution of GP and DSP • General Purpose Microprocessor traces roots back to Eckert, Mauchly, Von Neumann (ENIAC) • DSP evolved from Analog Signal Processors, using analog hardware to transform phyical signals (classical electrical engineering) • ASP to DSP because • DSP insensitive to environment (e.g., same response in snow or desert if it works at all) • DSP performance identical even with variations in components; 2 analog systems behavior varies even if built with same components with 1% variation • Different history and different applications led to different terms, different metrics, some new inventions • Convergence of markets will lead to architectural showdown

  21. Embedded System Runs a few applications often known at design time Not end-user programmable Operates in fixed run-time constraints, additional performance may not be useful/valuable Differentiating features: power cost speed (must be predictable) Embedded Systems vs. General Purpose Computing - 1 General purpose computing • Intended to run a fully general set of applications • End-user programmable • Faster is always better • Differentiating features • speed (need not be fully predictable) • cost (largest component power)

  22. DSP vs. General Purpose MPU • DSPs tend to be written for 1 program, not many programs. • Hence OSes are much simpler, there is no virtual memory or protection, ... • DSPs sometimes run hard real-time apps • You must account for anything that could happen in a time slot • All possible interrupts or exceptions must be accounted for and their collective time be subtracted from the time interval. • Therefore, exceptions are BAD. • DSPs have an infinite continuous data stream

  23. DSP vs. General Purpose MPU • The “MIPS/MFLOPS” of DSPs is speed of Multiply-Accumulate (MAC). • DSP are judged by whether they can keep the multipliers busy 100% of the time. • The "SPEC" of DSPs is 4 algorithms: • Inifinite Impule Response (IIR) filters • Finite Impule Response (FIR) filters • FFT, and • convolvers • In DSPs, algorithms are important: • Binary compatability not an issue • High-level Software is not (yet) important in DSPs. • People still write in assembly language for a product to minimize the die area for ROM in the DSP chip.

  24. TYPES OF DSP PROCESSORS • DSP Multiprocessors on a die • TMS320C80 • TMS320C6000 • 32-BIT FLOATING POINT • TI TMS320C4X • MOTOROLA 96000 • AT&T DSP32C • ANALOG DEVICES ADSP21000 • 16-BIT FIXED POINT • TI TMS320C2X • MOTOROLA 56000 • AT&T DSP16 • ANALOG DEVICES ADSP2100

  25. Architectural Features of DSPs • Data path configured for DSP • Fixed-point arithmetic • MAC- Multiply-accumulate • Multiple memory banks and buses - • Harvard Architecture • Multiple data memories • Specialized addressing modes • Bit-reversed addressing • Circular buffers • Specialized instruction set and execution control • Zero-overhead loops • Support for MAC • Specialized peripherals for DSP

  26. DSP Data Path: Arithmetic • DSPs dealing with numbers representing real world=> Want “reals”/ fractions • DSPs dealing with numbers for addresses=> Want integers • Support “fixed point” as well as integers . -1 Š x < 1 S radix point . –2N–1 Š x < 2N–1 S radix point

  27. DSP Data Path: Precision • Word size affects precision of fixed point numbers • DSPs have 16-bit, 20-bit, or 24-bit data words • Floating Point DSPs cost 2X - 4X vs. fixed point, slower than fixed point • DSP programmers will scale values inside code • SW Libraries • Separate explicit exponent • “Blocked Floating Point” single exponent for a group of fractions • Floating point support simplify development

  28. DSP Data Path: Overflow • DSP are descended from analog : • Modulo Arithmetic. • Set to most positive (2N–1–1) or most negative value(–2N–1) : “saturation” • Many algorithms were developed in this model

  29. DSP Data Path: Multiplier • Specialized hardware performs all key arithmetic operations in 1 cycle • 50% of instructions can involve multiplier=> single cycle latency multiplier • Need to perform multiply-accumulate (MAC) • n-bit multiplier => 2n-bit product

  30. Multiplier Multiplier Shift ALU ALU Accumulator Accumulator G DSP Data Path: Accumulator • Don’t want overflow or have to scale accumulator • Option 1: accumalator wider than product: “guard bits” • Motorola DSP: 24b x 24b => 48b product, 56b Accumulator • Option 2: shift right and round product before adder

  31. DSP Data Path: Rounding • Even with guard bits, will need to round when store accumulator into memory • 3 DSP standard options • Truncation: chop results=> biases results up • Round to nearest: < 1/2 round down,  1/2 round up (more positive)=> smaller bias • Convergent: < 1/2 round down, > 1/2 round up (more positive), = 1/2 round to make lsb a zero (+1 if 1, +0 if 0)=> no biasIEEE 754 calls this round to nearest even

  32. DSP Processor Specialized hardware performs all key arithmetic operations in 1 cycle. Hardware support for managing numeric fidelity: Shifters Guard bits Saturation Data Path Comparison General-Purpose Processor • Multiplies often take>1 cycle • Shifts often take >1 cycle • Other operations (e.g., saturation, rounding) typically take multiple cycles.

  33. 320C54x DSP Functional Block Diagram

  34. DSP Algorithm Format • DSP culture has a graphical format to represent formulas. • Like a flowchart for formulas, inner loops, not programs. • Some seem natural:  is add, X is multiply • Others are obtuse: z–1 means take variable from earlier iteration. • These graphs are trivial to decode

  35. DSP Algorithm Notation • Uses “flowchart” notation instead of equations • Multiply is or X • Add is or + • Delay/Storage is or or Delay z–1 D

  36. FIR Filtering: A Motivating Problem • M most recent samples in the delay line (Xi) • New sample moves data down delay line • “Tap” is a multiply-add • Each tap (M+1 taps total) nominally requires: • Two data fetches • Multiply • Accumulate • Memory write-back to update delay line • Goal: 1 FIR Tap / DSP instruction cycle

  37. FINITE-IMPULSE RESPONSE (FIR) FILTER . . . .

  38. FIR filter on (simple) General Purpose Processor loop: lw x0, 0(r0) lw y0, 0(r1) mul a, x0,y0add y0,a,b sw y0,(r2) inc r0 inc r1 inc r2 dec ctr tst ctr jnz loop • Problems: Bus / memory bandwidth bottleneck, control code overhead

  39. Instruction Memory Data Memory First Generation DSP (1982): Texas Instruments TMS32010 • 16-bit fixed-point • “Harvard architecture” • separate instruction, data memories • Accumulator • Specialized instruction set • Load and Accumulate • 390 ns Multiple-Accumulate (MAC) time; 228 ns today Processor Datapath: Mem T-Register Multiplier P-Register ALU Accumulator

  40. TMS32010 FIR Filter Code • Here X4, H4, ... are direct (absolute) memory addresses: LT X4 ; Load T with x(n-4) MPY H4 ; P = H4*X4 LTD X3 ; Load T with x(n-3); x(n-4) = x(n-3); ; Acc = Acc + P MPY H3 ; P = H3*X3 LTD X2 MPY H2 ... • Two instructions per tap, but requires unrolling

  41. Micro-architectural impact - MAC element of finite-impulse response filter computation X Y MPY ADD/SUB ACC REG

  42. 1 3 Xn 5 Yn X S b 2 6 aYn-1 D X a 4 Mapping of the filter onto a DSP execution unit • The critical hardware unit in a DSP is the multiplier - much of the architecture is organized around allowing use of the multiplier on every cycle • This means providing two operands on every cycle, through multiple data and address busses, multiple address units and local accumulator feedback 6 4 2 1 D 5 3

  43. MAC Eg. - 320C54x DSP Functional Block Diagram

  44. DSP Memory • FIR Tap implies multiple memory accesses • DSPs want multiple data ports • Some DSPs have ad hoc techniques to reduce memory bandwdith demand • Instruction repeat buffer: do 1 instruction 256 times • Often disables interrupts, thereby increasing interrupt response time • Some recent DSPs have instruction caches • Even then may allow programmer to “lock in” instructions into cache • Option to turn cache into fast program memory • No DSPs have data caches • May have multiple data memories

  45. Conventional ``Von Neumann’’ memory

  46. HARVARD MEMORY ARCHITECTURE in DSP PROGRAM MEMORY Y MEMORY X MEMORY GLOBAL P DATA X DATA Y DATA

  47. DSP Processor Harvard architecture 2-4 memory accesses/cycle No caches-on-chip SRAM Memory Architecture Comparison General-Purpose Processor • Von Neumann architecture • Typically 1 access/cycle • Use caches Program Memory Processor Processor Memory Data Memory

  48. Eg. TMS320C3x MEMORY BLOCK DIAGRAM - Harvard Architecture

  49. Eg. 320C62x/67x DSP

  50. DSP Addressing • Have standard addressing modes: immediate, displacement, register indirect • Want to keep MAC datapth busy • Assumption: any extra instructions imply clock cycles of overhead in inner loop=> complex addressing is good=> don’t use datapath to calculate fancy address • Autoincrement/Autodecrement register indirect • lw r1,0(r2)+ => r1 <- M[r2]; r2<-r2+1 • Option to do it before addressing, positive or negative

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