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(Subset) of ‘obvious’ Strip relevant architectures

(Subset) of ‘obvious’ Strip relevant architectures. Assume parallel strips forward and barrel Pixels with amplifier/discriminator – are individual trims needed Logical OR at strip end – area? 1% dead in 2.5cm long strip – recovery time 25mm/pixel length x 25ns (?x3)

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(Subset) of ‘obvious’ Strip relevant architectures

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  1. (Subset) of ‘obvious’ Strip relevant architectures

  2. Assume parallel strips forward and barrel Pixels with amplifier/discriminator – are individual trims needed Logical OR at strip end – area? 1% dead in 2.5cm long strip – recovery time 25mm/pixel length x 25ns (?x3) ABCn modified to accept digital signal – very similar design to existing barrel Thinned sensors – post processed with metal to help with routing? Either uncut 10 x 10 with reticule sized strips or Assembled 10 x 10 on thin substrate – how large gaps? Voltage – 20V ? Operating temperature – 20C ? Power – 10W/(10x10) sensor ? Some x0 gain, possible cost gain – sensors – HV system – Possible stability gain – warm operation Reticules or separated Simplest (change/to implement) Architecture Stitching of ‘marginal’ value? Issues pertinent to all architectures, not repeated

  3. Most Advanced Architectures Integrate ABCn into sensor Above pixel/strips – or to side would be a good geometry – requires stitching? Hybrid to connect ABCs between reticules or separated sensors, caps, power.. Triggerless Readout Abandon ABC as too complex to integrate on schedule Group strips into ~100s, pixel has short data driven pipe (like PiMMs) sparsify and ship out to local VL – need one 450Mbit/s output per 100 strips Bandwidth wise, ~3 VLs per 10 x 10 area Can sparsification and part of VL function be added at edge of sensor? Is this simpler/faster to implement than ABC integration? How much area at edge of strips to do logic - acceptable dead area? Significant x0 gain ‘ABC’ sensor 450Mbit/s copper to VL Mass of VL may be an Issue Close but not necessarilypractical 100 strip Sparsification/VL conversion Local VL

  4. 10cm x 10cm ‘sensor’ 2.5cm x 80mm synthesised strips 48 groups of ~ 100 strips ~ 5k strips x 40MHz = 200Gbit/s X 1% = 2Ghit/s X (ln(100)/ln2 + ln(16)/ln2) = 22Gbit/s 7 + 4 22G/48 = 458Mbit/s copper line Vertical pair, 100mm track and gap w = 200 x 48 = 9.6mm This is very close for a 10 module stave, and difficult for 13. But not a mile away. Embedded sparsification/short pipe 458Mbit/s copper line per 100 strips 100mm gap and track 2 x 10Gbit/s link per module [~50k links total cf CMS]

  5. Intermediate Architectures Stereo And axial hybrids Both coordinates from single sensor Gang logical output from pixel in different directions Simulated stereo Use ABCn modified to take digital input Same issues as simplest implementation Add logic in pixel to generate address – how many bits (1mm resolution?) Modify ABCn to store ? 5 bits rather than one per hit. Can this be done without making a strip dead for 5 crossings? Is five times larger pipeline realistic in ABCn Map outputs into a version of FEI4/5 chips? Significant x0 gain Geometry?

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