Biologically Inspired Computing, Nanoelectronic (Molecular Scale) Architectures

1. Biologically Inspired Computing, Nanoelectronic (Molecular Scale) Architectures Dr. Dan Hammerstrom http://web.cecs.pdx.edu/~strom// As we move to deep submicron and on to molecular scale circuits, IC design is challenging designers with unacceptable power density, unreliable components, quantum side effects, expensive interconnect, probabilistic behavior, etc. Alleviating these shortcomings will require new architectures and computational models.  Motivated by the fact that biological systems have successfully dealt with similar issues, we are using biological models as a guide to develop new models of computation and architectures that are more suitable to molecular scale electronics. Past and current support comes from National Science Foundation (NSF), Defense Advanced Research Projects Agency (DARPA), Office of Naval Research (ONR) and MaxViz, Inc. / USAF. • Selected Publications • D. Hammerstrom, "Post-CMOS - Biologically Inspired Computing," GOMAC Tech 05, March 2005, Las Vegas, Nevada. • C. Luk, C. Gao, D. Hammerstrom, M. Pavel, D. Kerr, "Biologically Inspired Enhanced Vision System (EVS) for Aircraft Landing Guidance," International Joint Conference on Neural Networks, Budapest Hungary, July 2004. • C. Gao, D. Hammerstrom, S. Zhu, M. Butts, "FPGA Implementation Of Very Large Associative Memories - Scaling Issues," Chapter submitted for book, FPGA Implementations of Neural Networks, Ed. Amos Omondi, Kluwer Academic Publishers, Boston, 2003. • C. Gao, D. Hammerstrom, "Platform Performance Comparison of PALM Network on Pentium 4 and FPGA," IJCNN 03, July 2003. • S. Zhu, D. Hammerstrom, "Reinforcement Learning in Associative Memory," IJCNN 03, July 2003. • S. Zhu, D. Hammerstrom, "Simulation of Associative Neural Networks," Proceedings of the International Conference on Neural Information Processing, November 2002, Singapore. • D. Hammerstrom, "Digital VLSI for Neural Networks," The Handbook of Brain Theory and Neural Networks, Second Edition, Ed. Michael Arbib, MIT Press, 2003. • D. Hammerstrom, "The Coming Revolution: The Merging of Computational Neural Science and Semiconductor Engineering," Toward Replacement Parts for the Brain, Ed. Ted Berger, MIT Press. • S. Rehfuss and D. Hammerstrom, "Comparing SFMD and SPMD Computation for On-Chip Multiprocessing of Intermediate Level Image Understanding Algorithms," Proceedings of the conference for Computer Architectures for Machine Perception 1997, Boston MA, October 1997. • D. Hammerstrom, D. Lulich, "Image Processing Using One-Dimensional Processor Arrays," The Proceedings of the IEEE, Vol. 84, No. 7, July 1996, pp. 1005-1018. • D. Hammerstrom, "A Digital VLSI Architecture for Neural Network Emulation, Pattern Recognition, and Image Processing," Naval Research News, Office of Naval Research, Three/1995 Vol. XLVII, pp. 27-43. • D. Hammerstrom, S. Rehfuss, "Silicon Cortex: The Impossible Dream?" Proceedings of the International Conference on Neural Information Processing - 94, Seoul, Korea, October 1994. • D. Hammerstrom, "Working with Neural Networks," IEEE Spectrum, July 1993, pp. 46-53. • D. Hammerstrom, "Neural Networks At Work," IEEE Spectrum, June 1993, pp. 26-32. • D. Hammerstrom, W. Henry, M. Kuhn, "The CNAPS Architecture for Neural Network Emulation," Parallel Digital Implementations of Neural Networks, Edited by K.W. Przytula  and V.K. Prasanna Kumar, Prentice Hall, Engelwood Cliffs, NJ, pp. 107-138, 1993. • D. Hammerstrom, "A Massively Parallel Architecture for Cost-Effective Neural Network Pattern Recognition, Image-Processing, and Signal-Processing," GOMAC 92 (Government Microcircuit Applications Conference), Las Vegas, NV, November 1992, Received "Meritorious Paper" award. • E. Means, D. Hammerstrom, "Piriform Model Execution on a Neurocomputer," Proceedings of the International Joint Conference on Neural Networks, pp. I-569 through I-574, Seattle, Washington, July 1991