MICROSYSTEMS LABORATORY DEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERING

1. MICROSYSTEMS LABORATORY DEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERING Microelectronic Hysteresis Robert W. Newcomb Talk for FICAMC: Plovdiv August, 16, 2008 (Fifth International Conference of Applied Mathematics and Computing – Bulgaria’2008)

2. 2 The Old Town of Plovdiv byIvan Theofilov • Your ancient floors float among the stars.Blue donkeys graze the silence around.The Roman road leads down along matrimonial chandeliers.A cry out of woman's flesh calls in the clock.Violet-colored philistines go to bed in the deep houses,they hear the pig, the hens, the train, the mouse.The darkness dawns with quick sensual pupils.The bridal veil flies away with the chimney's breath.Blue donkeys run on the moonlit roofs.Saints take off in a cloud from whitewashed churches,with blood-soaked lambs they welcome the bridal veil.Leopards gaze with amber eyes from the doorsteps.Among box trees bacchantes with satin bandspour fragrant myrrh out of bronze rhytons ... Ivan Theofilov was born in Plovdiv in 1931 and graduated from the Theatre Academy in Sofia. He is an honorary citizen of Plovdiv. The poem translated here is from Geometry of the Spirit, published by Free Poetic Society, Sofia, 1996, and translated by Zdravka Mihaylova

3. 3 Main topic of talk The mathematics for the design of VLSI CMOS circuits for hysteresis controlled by a voltage or current. Possible uses: Chaotic circuits, robust oscillators, memory, debouncing, pixel holding, emulation of chemical reactions, artificial neural networks, buildings in earth quakes Items for discussion: Microlectronic hysteresis concept The main idea, curve with movable load line Representation via semistate equations Key circuits used Some examples

4. 4 The concept for microelectronics Hysteresis (ancient Greek = to lag behind) • Static: piecewise multi/single valued [reason Spice won't run DC analysis on hysteresis] along with b) Dynamic: single valued given initial conditions Typical (static): binary bent

5. 5 Binary hysteresis curves

6. 6 Example of use for holding pixels in presence of noise

7. 7 Main Idea Slide a load line, which depends upon the hysteresis input parameter, across a nonlinear function to give two or more intersections in one region. ==>

8. 8 CMOS circuit and bent V-I hysteresisusing inverters

9. 9 CMOS bent hysteresis design curves

10. 10 Designing all CMOS V-I hysteresis

11. 11 CMOS inverter bent hysteresis

12. 12 Hysteresis use in chaos generation

13. 13 Multilevel hysteresis

14. 14 Typical binary hysteresis circuitOTA = operational transconductance amplifier= voltage controlled current source

15. 15 Variable hystereses

16. 16 4 quadrant current mode hysteresis

17. 17 Variable hysteresis from last circuit

18. 18 Hysteresis in several dimensions From UMCP dissertation of Yu Jiang

19. 19 Circuit to realize 2D hysteresis

20. 20 Dynamics via Semistate Equations Edx/dt = A(x) + Bu y = Cx u = input, y = output, x = semistate B, C, E constant matrices, E may be singular A(x) nonlinear to generate hysteresis

21. 21 Op-amp circuit for hysteresis

22. 22 Semistate equations for op-amp example

23. 23 OTA circuit for hysteresis

24. 24 OTA example semistate equations

25. 25 OTA CMOS circuit

26. 26 OTA curves

27. 27 Sliding load line on OTA curve

28. 28 Resulting OTA hysteresis, Iout vs Vin

29. 29 OTA VLSI layout

30. 30 Neural type cell circuit

31. 31 Neural type cell hysteresis

32. 32 CMOS resistor from OTA M3 M4 Floating resistor; can be positive or negative (by reversing green Leads to M1 & M2) M6 M10 M5 -Io(IR-) Io(IR+) M1 M2 V+ V- M9 M11 M7 M8 Vadj

33. 33 PSpice Simulation: Positive Floating Resistor Circuit • Observations • Linear I-V region centered at V+ – V- = 0V • IR+andIR- show good symmetry • Vadjmodulates I-V linearity range Vadj=-2.4v … -3.4v 0.6 magnified IR+ 1.0 0.3 0.5 IR+, IR- [A] 0.0 Vadj=-3.4v … -2.4v IR+, IR- [A] 0.0 IR- -0.3 -0.5 -1.0 -0.6 -6.0 -4.0 -2.0 0.0 2.0 4.0 6.0 -1.5 -0.75 0.0 0.75 1.5 V+ – V- [V] V+ – V- [V]

34. 34 Kinetic cells Plot for σ1=- σ2=1, ko=1=k2=2k1 u3=0.136 at = slopes Reference: V. Petrov, M. Peifer, J. Timmer, “Structural Stability Analysis of a Cell Cycle Control Model,” Comptes rendus de l’Academie bulgare des Sciences, Tome 58, No. 1, 2005, pp. 19 – 24.

35. 35 Circuit to give Iout=(Ix+Iy)2/(2Iw) Subtract Ix2/(2Iw) & Iy2/(2Iw)to get I=IxIy/Iw Iterate (= cascade connections) to get cubic, etc. W. Gai, H. Chen, E. Seevinck, “Quadratic-translinear CMOS Multiplier divider circuit,” Electronic Letters, May 1997, p. 860

36. 36 Configuration to give cubic products

37. 37 NPN differential pair Apply differential voltage Vd and tail current Io then Iout=I2-I1=Io·tanh(Vd/(2VT)), VT=thermal voltage=KT/Q I2+I1=Io => 2·I2=Io(1+tanh(Vd/2VT) 2·I1=Io(1-tanh(Vd/2VT)

38. 38 Multiplier via npn differential pairIout=(I4+I6)-(I3+I5) =Io·tanh(Vx/2VT)tanh(Vy/2VT)

39. 39 Cubic via npn differential pair: Iout=Io·tanh(vx)tanh(vy)tanh(vz) <=take diff=> <=from previous=>

40. 40 VLSI Transistors Two basic types with two complementary of each: MOSFET: NMOS & PMOS [piecewise square law] BJT: npn & pnp [exponential law]

41. 41 NMOS Law For VGS≤ Vth ID=0 off For VGS>Vth ID=b(VGS-Vth)2if VGS-VthVDS saturation =b(2(VGS-Vth)VDS-VDS2)if VGS-Vth<VDS Ohmic b=(mCox/2)(W/L) Ifl≠ 0 multiply by (1+lVDS); for now Vth>0

42. 42 Useful CMOS current circuits

43. 43 Setting up semistate equations Use graph theory: vb & ib = branch voltages and currents vt & il = tree voltages and link (cotree) currents KCL: 0t = Cib KVL: 0l= Tvb ==> vb = CTvtib = TTil ib=idevice+isource=id+is ; vb=vd+vs by equivalences for devices id=Y(vd)

44. 44 Useful equivalences

45. 45 Example of setting up equations Cutset equations = KCL at nodes I and II

46. 46 Device characterization

47. 47 Final semistate equations

48. 48 Idea of an extension In terms of binary hysteresis can set up a Preisach’s type of theory: Where h is binary hysteresis and w is a weight

49. 49 Alternate CMOS OTA hysteresis

50. 50 CMOS OTAVout/Vin hysteresis circuit