Exploring Computer Architecture Variations & Extensions

1. An Introduction to Informatics Chapter 6. Computer Architecture January 6, 2020 OSLab. Cho, Ho-Gi

2. Ch.6 Computer Architecture Contents • Programmer’s Specification • Data and Control Flows • Extensions and Variations

3. Ch.6 Computer Architecture Extensions and variations • Extensions on instruction set • computers have much larger instruction sets that are certainly sufficient for any computational task • typically from 64 to several hundred • classified in terms of the functional groupings; ex) p.115, table 6.1 • arithmetic • multiplication, division, decimal/floating point arithmetic • shift • circular shifts • logical • or, exclusive-or • move • move between two storage locations, swap or interchange of two words • etc.

4. Ch.6 Computer Architecture • Variations on instruction • many instruction variations result from the availability of more than one program-accessible register • operand addressing methods • world length of the machine • number of operand • etc.

5. OP code X instruction low X data high Ch.6 Computer Architecture • Operand Addressing Methods • Direct addressing • the operand address directly appears in the computer instruction • ex) ADD X

6. OP code X low instruction instruction X branch instruction high Ch.6 Computer Architecture • Relative addressing • an operand field of an instruction contains a displacement relative to the address of the instruction • ex) B +15, BZ -4

7. OP code OP code data [X] instruction instruction low X Y address Y data high Ch.6 Computer Architecture • Immediate addressing • the operand itself, not its address, appears in the instruction • ex) LS 2 • Indirect addressing • The address of the address of the operand is stored in the operand field • ex) LD [A]

8. Ch.6 Computer Architecture • Indexed Addressing sum := 0 for i = 1 upto 20 do sum := sum + x[i]

9. Ch.6 Computer Architecture • Word length of the machine • from 8bits to 64bits • Number of operands • Three-address • for the arguments • ADD X Y Z; [X] ← [Y] + [Z] • BEQ X Y L; if [X] = [Y] then go to L • Two-address • to specify operand and result locations • ADD X Y; [X] ← [X] + [Y] • One-address • SAM is an example of a one-address machine • Zero-address • accessed from fixed resisters or addressed by registers • ADD ; [R1] ← [R1] + [R2] // hardware “stacks”

10. Ch.6 Computer Architecture • Auxiliary Storage (p.128, Fig 6-8) • provides a large temporary or permanent repository for files of data and programs • Input/Output control • fast speed of CPU and main storeVSslow speed of IO device • Input/output operations overlap the other operations • Communication between the CPU and IO system • polling Hey!, Do you complete? I/O system CPU

11. Ch.6 Computer Architecture • Interrupts Hey! I complete! I/O system CPU cycle : Fetch next instruction; ic := ic + 1; Execute instruction; {Change ic, if the Interrupt resister is set.} if Interrupt then ic := InterruptLocation; go to cycle; The Instruction Cycle including Interrupt cycle