1 / 2

Write Clock (MCk) 40 Mhz

WRITE. Write Clock (MCk) 40 Mhz. Trig_x - (low: sampling window controls writing to sampling cells). width ~ 15 ns, trig to low just before clock rising edge. A/D CONVERSION. Clear_ADC (pulse clears register). width ~ 20 ns (sometime before ADC). Rp (pulse clears Cext).

gomer
Download Presentation

Write Clock (MCk) 40 Mhz

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. WRITE Write Clock (MCk) 40 Mhz Trig_x - (low: sampling window controls writing to sampling cells) width ~ 15 ns, trig to low just before clock rising edge A/D CONVERSION Clear_ADC (pulse clears register) width ~ 20 ns (sometime before ADC) Rp (pulse clears Cext) width ~ 20 ns (falling edge coinciding with ADC start) Ctrl_rd_x width ~ 2 us (time for ADC conversion) READ delta t (~ 5ns) Read Clock (Ck_rd) 40 Mhz . . . . width ~ 10 ns, sometime before passing token Clear_token width ~ 6.5 us (time to read out 256 cells) AD_x Tok_in must trigger on a read clock leading edge, width= 2*delta t

  2. READ Read Clock (Ck_rd) 40 Mhz

More Related