DIGITAL II Microprocessors & Embedded Systems

1. DIGITAL II Microprocessors & Embedded Systems ECE 0909.242.01 Week 4 Custom Single Purpose Processors: Hardware Robi Polikar, Ph.D. John L. Schmalzel, P.E., Ph.D.

2. Outline • Introduction • Combinational logic • Sequential logic • Custom single-purpose processor design • RT-level custom single-purpose processor design Chapter 2: Custom single-purpose processors

3. Custom single-purpose processor basic model external data inputs external control inputs … … controller datapath registers next-state and control logic functional units state register … … external data outputs external control outputs a view inside the controller and datapath external control inputs external data inputs … … datapath control inputs controller datapath datapath control outputs … … external control outputs external data outputs controller and datapath • Store and manipulate system data • registers • functional units • wires • multiplexers Control datapath I/O Monitor external I/O

4. Example: greatest common divisor int x,y !1 1: (a) black-box view 1 !(!go_i) 2: !go_i x_i GCD go_i y_i 2-J: 3: x = x_i d_o 4: y = y_i !(x!=y) 5: x!=y 6: x<y !(x<y) y = y -x x = x - y 7: 8: 6-J: 5-J: d_o = x 9: 1-J: • Describe in words  Behavioral design • Determine I/O Black box view • Create algorithm • Convert algorithm to “complex” state machine • Known as FSMD: finite-state machine with datapath Essentially a flow chart • Different than earlier state diagrams • Arithmetic expressions are allowed • Other variables are allowed • Can use templates to perform such conversion Our single purpose is to design a GCD! (c) state diagram (b) desired functionality How would you implement a GCD in software?

5. State diagram templates Branch statement if (c1) c1 stmts else if c2 c2 stmts else other stmts next statement !cond C: C: c1 !c1*!c2 !c1*c2 cond c1 stmts c2 stmts others loop-body- statements J: J: next statement next statement Assignment statement Loop statement while (cond) { loop-body- statements } next statement a = b next statement Action of this state a = b Condition state C next statement Loop body Join state J

6. Creating the datapath • Create a register for any declared variable  x, y, d • Create a functional unit for each arithmetic operation • Connect the ports, registers and functional units • Based on reads and writes • Connect “write’s” source to that variable’s register • A source may be an input port, functional unit or other registers • Use multiplexers for multiple sources • Create unique identifier • for each datapath component control input and output !1 1: 1 !(!go_i) 2: !go_i x_i y_i 2-J: Datapath 3: x = x_i 4: y = y_i 0: x 0: y !(x!=y) 5: x!=y 6: x<y !(x<y) y = y -x x = x - y 7: 8: 9: d 6-J: 5-J: d_o d_o = x 9: 1-J:

7. FSMDFSM • In order to implement this design, we need to convert the FSMD into a regular FSM that simply consists of Boolean functions and I/O variables (along with control I/O). • Essentially same structure as FSMD • Replace complex actions/conditions with datapath configurations • Replace every variable write by actions that set the select signals of the MUX in front of that variable’s register, such that the write’s source passes through the MUX, and assert the load signal of that register. • Replace every logical operation in a condition by the corresponding functional unit control output • Any signal that is not explicitly assigned a state, is implicitly assigned a zero (0), e.g., x_ld is assigned a 0 in every state, except for 3 and 8, where it is assigned a “1”

8. Creating the controller’s FSM x_ld y_ld d_ld go_i • Same structure as FSMD • Replace complex actions/conditions with datapath configurations • Replace every write by actions that set the select signals of the MUX in front of the variable’s reg., and assert the load signal of that reg. • Replace every logical operation in a condition by the corresponding functional unit control output Controller !1 !1 1: 1: 0000 1 !(!go_i) 1 !(!go_i) 0001 2: 2: !go_i !go_i 0010 2-J: 2-J: 0011 3: 3: x = x_i 4: y = y_i 0100 4: x_i y_i Datapath !(x!=y) 5: 0101 5: x!=y 0110 6: 6: 0: x 0: y x<y !(x<y) 7: 8: y = y -x x = x - y 7: 8: 0111 1000 6-J: 1001 6-J: 5-J: 1010 5-J: 9: d d_o = x 9: 1011 9: d_o 1-J: 1100 1-J:

9. Implementing the FSM Controller implementation model go_i x_sel Combinational logic y_sel x_ld y_ld x_neq_y x_lt_y d_ld Q3 Q2 Q1 Q0 State register I3 I2 I1 I0 • Complete the controller design by implementing the FSM we have just created • Use the standard sequential design techniques for this purpose • Complete the state diagram • Create the transition table • Generate Boolean functions from the transition table • Simplify the Boolean expressions, etc. • Note that in the previous design, there werea total of 13 states, which in general, requires 4 FFs  hence 4 state variables,I1, I2, I3, I4, with outputs Q1 ~ Q4.

10. Splitting into a controller and datapath go_i Controller !1 1: 0000 1 !(!go_i) 0001 2: !go_i 0010 2-J: x_sel x_sel = 0 x_ld = 1 0011 3: y_sel x_ld y_sel = 0 y_ld = 1 0100 4: x_i y_i Controller implementation model y_ld Datapath x_neq_y=0 0101 5: go_i x_sel Combinational logic n-bit 2x1 n-bit 2x1 x_neq_y=1 y_sel 0110 6: x_ld x_lt_y=1 x_lt_y=0 y_ld x_neq_y 0: x 0: y y_sel = 1 y_ld = 1 x_sel = 1 x_ld = 1 7: 8: x_neq_y x_lt_y 0111 1000 x_lt_y d_ld 1001 6-J: d_ld != < subtractor subtractor 1010 5-J: 5: x!=y 6: x<y 8: x-y 7: y-x d_ld = 1 1011 9: Q3 Q2 Q1 Q0 9: d 1100 1-J: State register I3 I2 I1 I0 d_o

11. Controller state table for the GCD example Inputs ControllerI/P variables ControllerO/P variables Outputs Next statevalues Current statevalues go_i x_ld y_ld d_ld x_sel y_sel x_lt_y x_neq_y Q3 Q2 Q1 Q0 I3 I2 I1 I0 0 0 0 0 * * * 0 0 0 1 X X 0 0 0 0 0 0 1 * * 0 0 0 1 0 X X 0 0 0 0 0 0 1 * * 1 0 0 1 1 X X 0 0 0 0 0 1 0 * * * 0 0 0 1 X X 0 0 0 0 0 1 1 * * * 0 1 0 0 0 X 1 0 0 0 1 0 0 * * * 0 1 0 1 X 0 0 1 0 0 1 0 1 0 * * 1 0 1 1 X X 0 0 0 0 1 0 1 1 * * 0 1 1 0 X X 0 0 0 0 1 1 0 * 0 * 1 0 0 0 X X 0 0 0 0 1 1 0 * 1 * 0 1 1 1 X X 0 0 0 0 1 1 1 * * * 1 0 0 1 X 1 0 1 0 1 0 0 0 * * * 1 0 0 1 1 X 1 0 0 1 0 0 1 * * * 1 0 1 0 X X 0 0 0 1 0 1 0 * * * 0 1 0 1 X X 0 0 0 1 0 1 1 * * * 1 1 0 0 X X 0 0 1 1 1 0 0 * * * 0 0 0 0 X X 0 0 0 1 1 0 1 * * * 0 0 0 0 X X 0 0 0 1 1 1 0 * * * 0 0 0 0 X X 0 0 0 1 1 1 1 * * * 0 0 0 0 X X 0 0 0

12. Other issues… • There are a total of 7 inputs to the controller 128 rows for TT • Reduce number of rows, using * for some I/P combinations • Tedious to optimize by hand • Use CAD tools ! • CAD tools that automatically generate digital gates from sequential programs (behavioral design), FSMDs or FSMs or logic equations are known as sythesis tools. • Data path can also be further optimized: • Merge functional units (one instead of two subtractors), but we would then need more multiplexers. • Merge certain states into single states • Be careful about timing issues: • All statements in a single state are implemented concurrently in an FSMD! • Actions consisting of writes to variables do NOT actually update the variables until after the next clock cycle, since all variables are implemented as registers. Assuming that an outgoing arc from a state is using the updated value is a very common mistake. If we want to assign a value to a variable, and then branch based on that value, we NEED to insert an additional state. This is what the empty states in FSMD are for.!

13. Completing the GCD custom single-purpose processor design … … controller datapath registers next-state and control logic functional units state register … … a view inside the controller and datapath • We finished the datapath • We have a state table for the next state and control logic • All that’s left is combinational logic design • This is not an optimized design, but we see the basic steps

14. Summary • Custom single-purpose processors • Straightforward design techniques • Can be built to execute algorithms • Typically start with FSMD • CAD tools can be of great assistance