Rich Katz, Grunt Engineer NASA Office of Logic Design

1. Briefing: Independent NASA Test of RTSX-SU FPGAsIntroduction Rich Katz, Grunt Engineer NASA Office of Logic Design

2. Schedule and Logistics • 9:30 am Meeting starts • 12:30 pm Lunch. Buildings 1 and 21 have cafeterias • 1:45 pm Meeting resumes • Work until we're done Audio and video recording is not permitted.

3. Presenters John Campbell The Aerospace Corporation Frank Capps Northrop Grumman Space Technology Daniel K. Elftmann Actel Corporation Rich Katz NASA Office of Logic Design Noriko Yamada JAXA

4. Briefing Topics 10: Introduction 11: Comparison of A54SX-A/UMC and RTSX-SU Differences 12: Timing Analysis for MEC Tiger Team Results 20: Summary of NASA Experiment Results RT54SX-S/MEC RTSX-SU/UMC 21: KU1, KU2, KM1, KM2 Anomalies and Failure Analysis Update 22: Single S-Antifuse and Programming Update 23: KU3 and KU4 Plans 30: ESD Update: Process Improvements and ESD Mechanisms 40: Summary of The Aerospace Corporation Results 41: Long-term Test (A54SX-A/UMC) 42: Space Qualification Test (RTSX-SU) 50: FIT Rate Calculations of RTSX-SU/UMC FPGAs 60: Summary of JAXA Experiment Results 70: RTAX-S Qualification 80: Discussion: Post Programming Electrical Testing and Burn-In Risk vs. Rewards 90: Open Discussion

5. Family of SX-A, SX-S, and SX-SU FPGAs A54SX32A RTSX32SU RT54SX32S A54SX32A UMC UMC MEC MEC 0.22µm 0.25µm 0.25µm 0.25µm

6. A few application notes(based on recently observed “oopses”)

7. RCO’s

8. 0000 0 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8 1001 9 1010 10 1011 11 1100 12 1101 13 1110 14 1111 15 0000 16 A B C D D Q DFC1B CLR D Q DFC1B CLR D Q DFC1B CLR D Q DFC1B CLR Y TCNT AND 4 CLK CLK CLK CLK CLDCK ACLR Implementation Level Terminal count of a 4-bit synchronous counter.

9. Asynchronous DecodingGlitch Generation 01111111111111 10000000000000 … 11111111011111 11111111100000 Because of unequal propagation delays, the sequence can momentarily go through state 11111111111111 generating a glitch.

10. Clock skew

11. Q Q Q Q Q Q Q Q D D D D D D D D Clock Skew: Schematics

12. Clock Skew: VHDL Library IEEE; Use IEEE.Std_Logic_1164.All; Entity Skew Is Port ( Clk : In Std_Logic; D : In Std_Logic; Q : Out Std_Logic ); End Skew; Library IEEE; Use IEEE.Std_Logic_1164.All; Architecture Skew of Skew Is Signal ShiftReg : Std_Logic_Vector (31 DownTo 0); Begin P: Process ( Clk ) Begin If Rising_Edge (Clk) Then Q <= ShiftReg(0); ShiftReg (30 DownTo 0) <= ShiftReg (31 DownTo 1); ShiftReg (31) <= D; End If; End Process P; End Skew; Simple 32-bit element shift register

13. TH TROUTE TCQ FF2 FF1 Q Q D D TSKEW Clock Skew: Timing Model

14. NASA Meeting Summary • January 2004, Independent Assessment Team • Finding: Device overstress, testing issues • Finding: One residual antifuse failure. • April 2004, Design Seminar • Understanding, identification, and reduction of stress • July 2004, Briefing: Actel RTSX-S and RTSX-SU • RTSX-SU Introduced • September 2004, Briefing: RTSX-S and RTSX-SU • RT54SX-S antifuse failures in low-stress condition • Early RTSX-SU reliability data • February 2005, Briefing: Independent NASA Test of RTSX-SU FPGAs • ESD Sensitivity • February 2005, Briefing: Independent NASA Test of RTSX-SU FPGAs • Let’s get to work. • 2005 MAPLD International Conference - September, 2005

15. Upcoming Seminars • Pyrotechnic Initiators, Applications, and Lessons Learned (June 7, 2005) • "This is what we find in this stuff.” (July, 2005) • 2005 MAPLD International Conference Seminars (September 6, 2005) • Signal Integrity, Power Integrity, and Interfacing • Space Plug-and-play Avionics (SPA) Technical Committee/Workshop • Device Failure Modes and Reliability • Reconfigurable High-Performance Computing

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