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ECE 371 Microprocessor Interfacing

ECE 371 Microprocessor Interfacing. Unit 4b Memory Interfacing on the MC9S12DP256B Microcontroller. Operating Modes. • No External Addresses No External Data Buses Single Chip Stand Alone Mode Port A – General Purpose I/O Port B – General Purpose I/O Selected by:

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ECE 371 Microprocessor Interfacing

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  1. ECE 371Microprocessor Interfacing Unit 4b Memory Interfacing on the MC9S12DP256B Microcontroller

  2. Operating Modes • No External Addresses • No External Data Buses • Single Chip Stand Alone Mode • Port A – General Purpose I/O • Port B – General Purpose I/O • Selected by: - BKGD =1, MODB = 0, MODA = 0 • Operating Modes are Sensed at Reset Normal Single-Chip Mode

  3. Operating Modes Normal Expanded Wide Mode • Multiplexed 16-bit Address/16-bit Data Bus • Port A – High Address and Data Bits • Port B – Low Address and Data Bits • ADDR[7:0] and DATA[7:0] • Control Signals: R/W (from PE2) ECLK (from PE4) • Selected by: - BKGD =1, MODB = 1, MODA = 1

  4. Operating Modes Normal Expanded Narrow Mode • Multiplexed 16-bit Address/8-bit Data Bus • Port A – High Address and All 8 Data Bits- ADDR[15:8] and DATA[7:0] • Port B – Low Address • ADDR[7:0] • Control Signals: R/W (from PE2) ECLK (from PE4) • Selected by: - BKGD =1, MODB = 0, MODA = 1

  5. MULTIPLEXED WIDE BUS ADDR7 - ADDR0/ DATA7 - DATA0 PB7 - PB0 ADDR 15 - ADDR8/ DATA15 - DATA8 PA7 - PA0 PE2 R/W (EXTERNAL BUS CLOCK) PE4 ECLK LSTRB PE3

  6. MULTIPLEXED NARROW BUS ADDR7 - ADDR0 PB7 - PB0 PA7 - PA0 ADDR 15 - ADDR8/ DATA7 - DATA0 PE2 R/W PE4 ECLK

  7. Access Type vs. Bus Control Pins Table 12-5 Access Type vs. Bus Control Pins /LSTRB A0 R/W Type of Access 1 0 1 8-bit read of an even address 0 1 1 8-bit read of an odd address 1 0 0 8-bit write of an even address 0 1 0 8-bit write of an odd address 0 0 1 16-bit read of an even address 1 1 1 XXX 0 0 0 16-bit write to an even address 1 1 0 XXX

  8. Interface to 16-bit Data Bus A17 .. A1 A17 .. A1 /cs1 cs2 /oe /we /cs1 cs2 /oe /we 128K x 8 128K x 8 D15 .. D8 High Byte D7 .. D0 Low Byte

  9. ADDRESS LATCHES MC9SDP256B12 ADDR7 - ADDR0 PB7 - PB0 CLK ADDR 15 - ADDR8 PA7 - PA0 CLK ECLK PE4 ADDRESS LATCHED BY ON CLK

  10. DemultiplexedAddress ECLK ADR2 ADR3 ADR4 ADR1 DAT2 DAT3 DAT3 DAT1 Demultiplexed Address ADR1 ADR2 ADR3 ADR4

  11. PAGE ADDRESSING FOR EMULATION EXPANDED MODES MC9SDP256B12 PK5 - PK0 XADDR19 - XADDR 14 PK7 ECS (IF ECS = 0, USE XADDR19 - XADDR 14, ALONG WITH ADDR13 - ADDR0) (IF ECS = 1, USE ONLY ADDR15 - ADDR0)

  12. GENERATION OF READ AND WRITE SIGNALS FOR MEMORY INTERFACING ECLK WE R/W (WRITE) OE (READ)

  13. In the Normal Expanded Narrow Mode and the Normal Expanded Wide Mode, the Page Window Access Memory Region Can be Allocated Between External Memory and Internal Memory

  14. The ECS Signal is activated in the Emulation Expanded Narrow Mode and the Emulation Expanded Wide Mode when the Microcontroller Tries to Access Memory Through the Page Access Window Which Would Have Been Accessed Internally if the Normal Expanded Narrow Mode or the Normal Expanded Wide Mode, Respectively, Had Been Used.

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