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TRIP-t bench measurements

TRIP-t bench measurements. Leo Bellantoni D0 AFEII Director’s Review. The TRIP-t. The TRIP-t is the custom mixed-signal ASIC at the heart of the AFEII board Input is the VLPC-amplified pulse, plus timing signals Outputs [32, multiplexed] are: Digital discriminator pulse for triggering

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TRIP-t bench measurements

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  1. TRIP-t bench measurements Leo Bellantoni D0 AFEII Director’s Review

  2. The TRIP-t • The TRIP-t is the custom mixed-signal ASIC at the heart of the AFEII board • Input is the VLPC-amplified pulse, plus timing signals • Outputs [32, multiplexed] are: • Digital discriminator pulse for triggering • Analog O[1V] signal giving amplitude of VLPC pulse • Analog O[1V] signal giving time of VLPC pulse • Analog pulses through 48 bucket pipeline • Serial programming interface to set operating parameters via DACs • Test injection circuit

  3. Design goals • 100ns integration window typical, adjustable from 50 to 150ns • A-pulse adjustable gain: saturation 150fC at highest gain, 3000fC at lowest • t-pulse adjustable gain to cover integration window • Noise < 1fC referred to input • Analog pulse outputs uniform to 3%, 7 bit precision on amplitude, 2ns on time • 99% of discriminator turnons within 4fC; width <1fC • Discriminator thresholds 4-20fC typical in tracker; for preshower detector, want as high as practical • Power < 320mW

  4. SKIPB A-Pipeline 48 x 32 chan Analog MUX Q_TEST [1:33] A OUT Front End Q_IN [1:33] Dummy OUT [33] t-Pipeline 48 x 32 chan Analog MUX t OUT MUX_CLK PROG_IN MUX_RESET PROG_CTRL Prog Interface PROG_RESET DAC OUT PROG_CLOCK DISCRIM [0:31] Digital MUX DISCR_OUT PROG_OUT DIG_EN_L DIG_EN_U DIG_RESET A set of DAC values and timing diagrams for the control lines that feed into the chip that are close to final have been found and used.

  5. Frontend IBOPAMP A OUTPUT Q_TEST 200fF 80fF GAIN[2] 160fF V_REF Q_IN GAIN[1] 80fF IFFP2 GAIN[0] 40fF 1.0pF IB_T t OUTPUT 3.0fF 40fF GAIN[3] Z V_TH x10 RESET PLN_CLK V_REF IBOPAMP - + DISCRIM_OUT IFFP2 IBP IBOPAMP IBCOMP IFF - - - + + +

  6. Digital Discriminator outputs 99%  2.6s 2.6 x 0.6fC < 4fC 32 chans <1fC Turn-on curves fit (integrated) Gaussians nicely

  7. A-pulse outputs 32 chans Differential gain, V/Q It’s in the SPICE simulation too… Not linear at low outputs

  8. A-pulse outputs Vdda OUTAP OUTAPBUF Vbias V/Q Problem “occurs” in 2-FET output buffer at output of the analog pipeline.

  9. A-pulse outputs Vdda Vbias OUTAPBUF OUTAP Swapping n-channel FETs for p-channel FETs fixes it in simulation 7.6 bit accuracy

  10. A-pulse A -pulse gain distribution 9 = 8.326 m 8 = 0.066 s 7 6 5 4 3 2 1 0 8.2 8.4 8.16 8.24 8.28 8.32 8.36 8.44 8.48 8.52 8.56 mV/fQ 0.8% gain uniformity 55ns flat-top (3% less gain spread) for 100ns gate

  11. t-pulse outputs 32 chans A 2nd effect of the non-linearity Will set V/t to keep out of this region (2-20 mV/ns range) - this is final parameter setting issue Space for pedestal & gain already in database - both AFE on-board pulser and tracks available for calibration Residual for 50  t  110ns ~1ns RMS

  12. Time Walk • t / Q  55 mV/fC, corresponding to  44 ps/fC • T_OUT has large pulse-to-pulse fluctuations below ~20fC  2 p.e. over threshold A MIP at 90 corresponds to about 50fC (8 photoelectrons collected @ 40k gain)

  13. Design goals • 100ns integration window typical, adjustable from 50 to 150ns- Operated at 100ns w/no problems • A-pulse adjustable gain: saturation 150fC at highest gain, 3000fC at lowest- Obtained 90/2900fC Workable • t-pulse adjustable gain to cover integration window- OK out to ~300ns • Noise < 1fC referred to input- Measured <0.4fC • Analog pulse outputs uniform to 3%, 7 bit precision on amplitude, 2ns on time- Amplitude gains <1%, linearity needs to be fixed. Time gains OK, 1ns residuals • 99% of discriminator turnons within 4fC; width <1fC- Looks good, needs more stats • Discriminator thresholds 4-20fC typical in tracker; for preshower detector, want as high as practical- Operated at several settings between 5 and 10fC • Power < 320mW- Measured 265mW

  14. Conclusion • A prototype TRIP-t has been extensively bench tested and good operating parameters have been found. Further tests in quantity and with wider temperature variations are planned. • It is fully functional and with a simple modification should perform as required. The chip designer describes the modification as “minimal risk”. • We’ll need 5000 good packaged chips, and plan a joint submission with the FPIX chip on 20 May. (One version) • Chip packaging has been worked out, and there is even some documentation.

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