Power Supply Integrity: Measurement and Regulation of On-Chip Supply Noise

1. Power Supply Integrity: Measurement and Regulation of On-Chip Supply Noise Elad Alon

2. Evolution of Chip Design • Initially driven by limited number of transistors/chip • More recently, performance (freq.) was the #1 driver • Today, landscape has changed • Ex: Fastest circuits you can build would burn themselves up *Pictures from http://www.tomshardware.com/2001/09/17/hot_spot/

3. Emerging Integrated Circuit Issue: Power Supply Integrity • Significant time and resources spent on power distribution network: • ~70% of package pins just for power • Top 2-3 (thick) metal layers • Why has power delivery become this critical?

4. Scaling and Supply Impedance • CMOS scaling has led to lower supply voltages and constant (or increasing) power consumption Impedance Requirements of High-Performance Processors • This forces drastic drop in supply impedance • Even at constant power: • Vdd↓, Idd ↑  |Zrequired| ↓↓ • Today’s chips: • |Zrequired| ≈ 1 mΩ! • Hard to achieve across entire frequency spectrum • Supply voltage will be noisy Required Impedance (Ω) Technology (μm)

5. Impacts of Supply Noise • Variations on supply reduce digital performance • Impacts noise margins too, but digital gates generally robust • Supply noise can ruin analog signals • Most chips have some critical analog components • Many tools to estimate noise, but few measurements • Need measurement bandwidth of >10-20 GHz • 6 effective bits 20 GS/s ADC: 9 W

6. Outline • Motivation • Supply Noise Measurement • Regulation and Power Efficiency • Conclusions

7. Review of Previous Approaches • Sub-sampling to avoid high-speed interfaces or converters • Just like equivalent time oscilloscopes • Very good at measuring repetitive (deterministic) waveforms • Can also collect statistical distribution of noise • However, can’t measure “random” noise dynamics Real Time Sub-sampled

8. Measured Supply Noise from 90nm Itanium Microprocessor S. Naffziger, B. Stackhouse, T. Grutkowski, D. Josephson, J. Desai, E. Alon, and M. Horowitz, “The Implementation of a 2-Core, Multi-Threaded Itanium Family Processor,” Journal of Solid-State Circuits, Jan. 2006.

9. Measuring “Random” Supply Noise • Supply noise is basically deterministic • But extremely complicated to calculate • “Noise” is a label for a random process • Can be characterized by its frequency spectrum • Measure autocorrelation to find spectrum of supply noise • Extension of sub-sampling technique • Only needs 2 low rate samplers

10. Autocorrelation Review • Autocorrelation measures how correlated a process is with a delayed version of itself • For a stationary (time-invariant) process: • R() = E[V(t-/2)·V(t+/2)] • Power Spectral Density (PSD) is Fourier Transform of R(): Band-limited Noise: R(τ) PSD ω τ

11. V   Tsamp Measuring Autocorrelation • Don’t need V for all t • Just need sample pairs • Autocorrelation is an average property • Nyquist frequency set by minimum  • Not by sampling rate

12. Measurement System Block Diagram E. Alon, V. Stojanović, and M. Horowitz, “Circuits and Techniques for High-Resolution Measurement of On-Chip Power Supply Noise,” Journal of Solid-State Circuits, April 2005.

13. Sampler Implementation

14. VCO-based ADC • Simple, cheap ADC • Scan circuitry bigger than ADC • High Resolution • 1 LSB = 1/(TwinKVCO) • Can increase resolution with external averaging too • VCO random phase creates dither at quantizer input • Whitens the quantization noise • Bad accuracy • But don’t care since we’re calibrating

15. Processor Core 1MB L2I Power Controller 12MB L3 Cache Processor Core 90nm Itanium, Chip Designers Like Measurements… • Measurement circuits included in several chips from different companies: • Rambus (0.13 µm, 90 nm SOI), Intel/HP (90 nm, 45 nm), AMD (65 nm SOI), TI (90 nm), NEC (90 nm) • 1st chip: Rambus 0.13 µm serial transceiver • Could measure Vdd (link digital supply) and VddA (link analog supply) 12MB L3 Cache ASIC 4x 1-10 Gb/s Links 0.13 µm Link, 90nm SOI I/O, …

16. Measured PSD • Measured PSDs with system off (noise floor), then all 4 links running at 4 Gb/s • Peaks mostly from repetitive waveforms • 4 GHz on VddA: differential 2 GHz clock

17. Measured PSD (cont’d) • Random noise has some peaking on Vdd • Otherwise looks white • Saw periodic variations in the supply • Could random noise vary too?

18. Is Supply Noise Stationary? • Chip clocks may modulate noise • Ex: more switching at beginning of clock cycle than at end • Flip-flops all switch on rising edge • Noise not stationary • But, modulation is repetitive • Supply noise is cyclostationary • At same time point in each cycle, noise statistics are the same

19. Cyclostationary Noise Example • Measure PSD of random noise at two different times to see example behavior • Reduce link data-rate to 2 Gb/s to make cyclostationarity more apparent • Most digital logic quiet at end of the cycle

20. Measured Cyclostationary PSDs • Measurement verifies cyclostationary behavior • 1 GHz noise at t2, but not at t1 • Link clock is 1 GHz for this data-rate • Link relatively quiet at t1, active at t2

21. Sampler in Modern Technologies • Modern high-performance transistors very leaky • Don’t always get special low-leakage devices (cost) • Itanium sampling switch design: • Design moved towards higher analog complexity • Is there an easier, more “digital” way?

22. Averaging-Based Measurement • Exploit VCO dither: • Averaging dithered low-resolution samples can reconstruct waveforms and autocorrelation • Sampling switch was for long Twin (to get resolution) • Low resolution  short Twin • No need for sampling switch V. Abramzon, E. Alon, B. Nezamfar, and M. Horowitz, “Scalable Circuits for Supply Noise Measurement,” ESSCIRC, Sept. 2005.

23. Outline • Motivation • Supply Noise Measurement • Regulation and Power Efficiency • Conclusions

24. On-Chip Regulation • For supply integrity, two applications of regulation: • Isolating supply of sensitive analog blocks • Improving quality of digital supply • Worked on isolating regulator for PLLs* • Focus here on digital regulation • Even more challenging than regulation for analog *E Alon, J. Kim, S. Pamarti, K. Chang, and M. Horowitz, “Replica Compensated Linear Regulators for Supply-Regulated Phase-Locked Loops,” Journal of Solid-State Circuits. Feb. 2006.

25. Vnom 1 Vmin Supply Noise and Digital Logic Vdd • Since gate delay depends on Vdd: • To hit a desired frequency • Need to guarantee some minimum voltage • Supply variations force higher nominal voltage • Looks like another source of power loss • Can regulators be efficient enough to improve power by reducing noise? • Regulator power needs to be less than recovered power

26. Linear Regulators Series Regulator Chip - Vdd Load Vreg + Vref + - Shunt (Parallel) Regulator Chip - Load Vdd Vreg + Vref + -

27. - + Improved Efficiency with Series Regulator? Vdd • Clearly won’t meet efficiency goal: • Regulator doesn’t really change noise on Vdd • So still need same margin • But added an extra Vdrop from variable resistor… • Series regulator best suited for isolation • Extra impedance decouples Vreg from Vdd noise Vref Vdd Noise Vreg Vdrop Vreg Load

28. Vreg Ishunt + Vref Load - Improved Efficiency with Shunt Regulator? • Regulator can only pull current out of supply • To counter noise in both directions, need to burn significant static current • Again, clearly inefficient • Need to allow shunt to deliver energy to the load • Not just dissipate it Itotal max(Inoise) Iload Ishunt max(Inoise) 0

29. Push-Pull Shunt Regulator Vshunt • Use an additional, “shunt” supply to push current into Vreg • Regulator capable of countering large variations • But regulator loss set mostly by (significantly smaller) average variation • Similar to Active Clamp* for board VRMs • Build on previous work to improve on-die impedance Ipush Iload + Vreg - Vref Ipush Ipull + Load - 0 Ipull *A.M. Wu and S.R. Sanders, “An Active Clamp Circuit for Voltage Regulation Module (VRM) Applications,” Transactions on Power Electronics. Sept. 2001.

30. Regulator Design Challenges Vshunt • Vshunt isn’t free • Takes resources away from main supply • Increases loss Ipush + Vreg - Vref + Load - Ipull • Really need low quiescent output current • Otherwise regulator too inefficient • For noise performance, need GHz bandwidth, stable feedback • Makes control design critical

31. Allocating Resources for Shunt Supply • Limited number of pins, metal lines for power • Need to allocate resources between main and shunt supplies • For resistive losses: • If guarantee that Vshunt only handles transients • Resistive losses of main supply not too heavily affected • Need to be careful about shunt current flow path

32. Quiescent Output Current • Similar issues in RF and audio power amplifiers • In all cases, need to efficiently deliver energy based on a (small) input signal • Build on PA knowledge to achieve high efficiency: • Non-linearly switch the output power devices • Went to push-pull to minimize regulator power overhead • But many designs have significant Istatic Istatic

33. Switched-Output Regulator:Comparator Feedback with Dead-Band • Need to convert small signal on Vreg into full-swing to drive switch • Use comparator in feedback path • To avoid unnecessary limit cycle: • Offset thresholds to create dead-band

34. Feedback Delay • Can we exploit comparator’s properties to improve effective delay? • For optimal response to noise at output, feedback bandwidth is critical* • For non-linear loop, this translates into low tdelay *E. Alon and M. Horowitz, “Feedback Amplifier Design for CMOS Linear Regulators,” in preparation.

35. Linear Loop with Derivative Control • Addition of sτd to input cancels some of the phase shift from limited amplifier bandwidth • But, implementing derivative behavior (without inductors) requires reduction of DC gain • Limits usefulness in a linear loop

36. Derivative Feedback with Comparators • As long as comparators swing full-rail • Only shape of TF in front of comparators matters • “Gain” is restored by the comparators • Net effect of derivative: reduces impact of tdelay • Similar to “sliding mode control” used in switching DC-DC converters and other non-linear loops • But region of sliding behavior is small

37. Noise Reduction and Power Efficiency • Measured results from 65 nm SOI AMD test-chip: • Regulator reduces noise by ~30% • Reduces overall power dissipation by ~1% • Process still in development – transistors slow • Results match model with slow devices taken into account • Expect to reach ~50% noise and ~4% power reduction

38. Outline • Motivation • Supply Noise Measurement • Regulation and Power Efficiency • Conclusions

39. Conclusions • IC power supply integrity increasingly challenging area • Difficult to counter or even measure supply noise • Proposed solutions often combine concepts from many areas: • Autocorrelation-based noise measurement • Non-linearly controlled regulator to improve system robustness and power consumption

40. Acknowledgements • Prof. Mark Horowitz • Prof. Boris Murmann, Prof. Simon Wong, Prof. Roger Howe • MARCO C2S2 and AMD for funding support • Prof. Tom Lee, Prof. Bruce Wooley, Prof. Stephen Boyd, Prof. Claire Tomlin for teaching, Prof. Joseph Kahn for collaboration • Horowitz group, especially Vladimir, Valentin, Bita, Jaeha, Dinesh, Hae-Chang, Ken, Ron, Amir, Azita, Sam, Xiling, Stefanos, Dean, and admins Teresa, Ann, Penny • Rambus, particularly Fari, Ken, Sudhakar, Jared, Carl, Fred, Bruno • People at IBM, HP, AMD, and Intel, especially Kevin Nowka, Sam Naffziger, Doug Josephson, Sanjay Sethi, Mike Leary, Greg Taylor • Friends, particularly Andrew, Michelle, Viresh, Christina • My parents, brother, grandparents, and Meredith