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SVT detector electronics

SVT detector electronics. Mauro Villa INFN & Università di Bologna. Overview: - SuperB SVT open options - F.E. chips - FEB (pre-)design. Configuration and open options. Layer0. 20 cm. 30 cm. 40 cm. Layer Radius 0 ~1.5 cm 1 3.3 cm 2 4.0 cm

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SVT detector electronics

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  1. SVT detector electronics Mauro Villa INFN & Università di Bologna Overview: - SuperB SVT open options - F.E. chips - FEB (pre-)design

  2. Configuration and open options Layer0 20 cm 30 cm 40 cm LayerRadius 0 ~1.5 cm 1 3.3 cm 2 4.0 cm 3 5.9 cm 4 9.1 to 12.7 cm 5 11.4 to 14.6 cm Layer 0 • Striplets baseline option : • Better physics performance (lower material ~0.5% vs 1% hybrid pixel, MAPS or thin hybrid pixel in between but not yet mature!) • Upgrade to pixel (Hybrid or CMOS MAPS), more robust against background, foreseen for a second generation of Layer0 Triggered FE chips Layer 1-5 • Strip detectors (up to 37 cm long) Triggered or data push FE chip? Which chip?

  3. Pixel front-end chips (L0) Full design of a 256x192 pixel matrix (50 um pixel width) running at 70 MHz; Timestamping at 100 ns; output clock at 200 MHz Data push or data pull selectable working mode 2 1 X4

  4. Efficiency for triggered version In triggered mode, hits stay on matrix till readout (trg on TS) or clear -> increase of occupancy and dead area -> inefficiencies Reduction of bandwidth: from 2.6 Gbps to 40 Mbps (using standard test values: 100 MHz/cmq rate, 150 kHz trig rate, 0.3 us DAQ window) Eff(6 μs) = 98.16% 50 MHz clock 2.5 MHz trigger rate (demanding!)

  5. 1-st prototypes results Bus for pixel chips Aliminum on kapton 165 um • Pixel Bus Prototype measurements: • Thermal test on the BUS did not show problems up to 85-90 Centigrade • A typical impedance of ~ 60 Ohm confirmed • Crosstalk higher than simulated ~ 5 %  Measurements performed on various samples with same results • frequency response: • signal transferrred with no “digital errors” up to 200 MHz, on individual lines (pattern ex. 0000100) • if a random digital pattern is sent through 8 adjacent lines, than max frequency decreases at ~ 160 MHz (line lenght ~ 10 cm) M. Citterio 5 Apr. 2011 Mauro Citterio

  6. Bus for pixel chip - II • Pixel Bus second generation: • Layout details agreed • Production: it could have started week 7 •  Production conclusion estimate  8-10 week later • Cern suggestions: Review the signal layers: concern about 15 um Al layer and 75 um lines prefer a BUS with decreased thickness Adoption of Cu (3 um thick, 50 um wide) • Simulation performed • on a 1101 pattern (three aggressors and one victim, the “0” line) • The results refer to the longest stripline. Goal was to keep the crosstalk signal below +/- 200 mV • The maximum frequency is ~ 130 MHz • There is no optimal termination at the receiving end. • Driver and receiver are implemented using the IBIS models provided by Xilinx • BUS bandwidth is decreased by ~ 15 % • It is the worst case ? Two IC signals will share the same plane M. Citterio

  7. First thoughts on Strip/striplet chips Main wishes for a new strip chip: Highest possible efficiency for L0 application (225 MHz/cm2 hit rate) Small shaping time Fast ADC conversion or ToT measurement High time resolution for timestamping Approx 30 MHz time stamping in L0 Triggered version to reduce bandwidth Fast data output on a limited number of lines (reduced space on HDI)

  8. Readout chip for strips ~hit_rate * trig_latency Sparsifier strip #127 FE ADC Or ToT Ctrl logic Buf #k ... Buf #1 strip #0 FE ADC Or ToT Ctrl logic Buf #k ... Buf #1 BUF #1 Triggered hits only readout/slow control First buffering per strip then transfer triggered time stamps Re-use of digital readout logic developed for pixels

  9. Analog part: ENC, shaping time and efficiency estimates RC2CR shaping, ID=500 mA (current in the PA input device), L=200 nm, N-channel input device, analog dead time=2.4 tp V. Re SuperB Workshop, Frascati, April 4, 2011 9

  10. First guess on number of buffers required for L0 striplets/L1 strip Assume L0 @ 225 MHz/cm2, L1@5 MHz/cm2 L0 = 2 MHz/strip, L1=270 KHz/strip F. Morsani

  11. DAQ reading chain for L0-L5 HDI +Transition card+FEB+ROM DAQ chain independent on the chosen FE options Optical 1 Gbit/s Optical Link 2.5 Gbit/s ~50 cm FEB ROM LV1 High rad area 10Mrad/year Off detector low rad area Counting room Std electronics HDI and transition card to be designed. Which SerDes? 11

  12. SuperB-FEB Board schematics Gb ethernet VME? Large FPGA DAQ link 2.5 Gbit/s VME FPGA Or uCPU L1/Spare DAQ link 4x1 Gbit/s FE links FCTS interface Small FPGA 4x1 Gbit/s FE links ECS interface Memory Small FPGA 4x1 Gbit/s FE links Small FPGA FCTS, ECS protocols to be decided experiment-wide Large FPGA for data shipping and monitoring VME FPGA or uCPU might be included in the large FPGA.

  13. Optical link mezzanine card for EDRO Developed as a part of ATLAS/FTK project 4 optical links at 1 Gbit/s; FPGA Xilinx, 40/100 MHz clk (programmable) PCB realized; now mounting components on first prototype Usable as link test mezzanine in SuperB (from autumn)

  14. Conclusions Definition of a strips readout chip for SVT Experience from FSSR2 and MAPS chips Main feautures Data pull architecture Better S/N ratios (Charge or ToT measurements) Lower requirements on bandwidths Contra: no trigger primitives; Easier data handling on L0-L1 Planning the FEB design in progress Test elements in production phase 14

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