2011 ITRS Emerging Research Devices Working Group Face – to – Face Meeting

1. 2011 ITRS Emerging Research DevicesWorking GroupFace – to – Face Meeting Jim Hutchby – Facilitating San Francisco Marriott Hotel 55 Fourth Street Room – Salon 5 San Francisco, California Sunday July 10, 2011 9:00 a.m. – 6:00 p.m.

2. Emerging Research Devices Working Group • Hiroyugi Akinaga AIST • Tetsuya Asai Hokkaido U. • Yuji Awano Keio U. • George Bourianoff Intel • Michel Brillouet CEA/LETI • Joe Brewer U. Florida • John Carruthers PSU • Ralph Cavin SRC • An Chen GLFOUNDRIES • U-In Chung Samsung • Byung Jin Cho KAIST • Sung Woong Chung Hynix • Luigi Colombo TI • Shamik Das Mitre • Erik DeBenedictis SNL • Simon Deleonibus LETI • Bob Fontana IBM • Paul Franzon NCSU • Akira Fujiwara NTT • Christian Gamrat CEA • Mike Garner Intel • Dan Hammerstrom PSU • Wilfried Haensch IBM • Tsuyoshi Hasegawa NIMS • Shigenori Hayashi Matsushita • Dan Herr SRC • Toshiro Hiramoto U. Tokyo • Matsuo Hidaka ISTEK • Jim Hutchby SRC • Adrian Ionescu EPFL • Kiyoshi Kawabata Renesas Tech • Seiichiro Kawamura Selete • Suhwan Kim Seoul Nation U • Hyoungjoon Kim Samsung • Atsuhiro Kinoshita Toshiba • Dae-Hong Ko Yonsei U. • Hiroshi Kotaki Sharp • Mark Kryder INSIC • Zoran Krivokapic GLOBALFOUNDRIES • Kee-Won Kwon Seong Kyun Kwan U. • Jong-Ho Lee Hanyang U. • Lou Lome IDA • Hiroshi Mizuta U. Southampton • Kwok Ng SRC • Fumiyuki Nihei NEC • Ferdinand Peper NICT • Yaw Obeng NIST • Dave Roberts Nantero • Barry Schechtman INSIC • Sadas Shankar Intel • Atsushi Shiota JSR Micro • Satoshi Sugahara Tokyo Tech • Shin-ichi Takagi U. Tokyo • Ken Uchida Toshiba • Thomas Vogelsang Rambus • Yasuo Wada Toyo U. • Rainer Waser RWTH A • Franz Widdershoven NXP • Jeff Welser NRI/IBM • Philip Wong Stanford U. • Dirk Wouters IMEC • Kojiro Yagami Sony • David Yeh SRC/TI • Hiroaki Yoda Toshiba • In-K Yoo SAIT • Victor Zhirnov SRC

3. Emerging Research Devices Working GroupMeeting Objectives 2011 ITRS ERD Chapter Preparation • Review administrative aspects • Deliverables and revised time line • Chapter outline and page count • Review the Emerging Memory, Logic & Architecture Sections • Table Content (Current & projected tables) • Major device research needs & technical barriers • Key materials scientific and/or technological issues • Thrust, tone & structure of the draft section • Critical Review Section • Review the Difficult Challenges Section • Review Scope and Taxonomy Sections • Review content of the Guiding Principles Section • Decide messages for the Public Presentation

4. 8:30 Light Continental Breakfast 9:00 Welcome and Introductions 9:10 Review meeting objectives & agenda Hutchby 9:30 Review status of ERD Chapter Hutchby Deliverables and Timeline Chapter Organization & Status Decisions made 9:45 Complete Memory, Logic, More-than-Moore, and Architecture, Sections Table Content (Current & projected tables) Major Research Needs & Technical Barriers Thrust, Tone & Structure of the Draft Section 9:45 Logic and Information Processing Section Bourianoff 11:00 Break 11:15 Memory Section Zhirnov ITRS ERD WG Meeting – July 10, 2011Agenda

5. 12:30 Working Lunch 1:15 More-than-Moore Brillouet 1:45 Architecture Section Cavin/Asai 2:30 Review Materials Chapter Related to ERD Garner 3:45 Introduce Initial Results of Memory & Logic Hutchby Critical Review & Benchmarking Welser 4:45 Review Difficult Challenges Hutchby 5:00 Review Scope and Taxonomy Sections Hutchby 5:15 Review Guiding Principles Section Bourianoff 5:30 Decide Messages of ERD Public Presentation Hutchby 6:00 Adjourn Meeting ITRS ERD WG Meeting – July 10, 2011Agenda

6. Scope (1 page) Difficult Challenges (1) Taxonomy Chart (1) Devices Memory Devices (13) Logic Devices (15) More than Moore (5) Architectures (12) Critical Assessment (8) Fundamental Guiding Principles (1) References (15) Total Pages (72) Draft ERD Chapter Outline

7. ERD Function Leader Chapter Chair – North America Hutchby Chapter Co-chair – Japan ERD Uchida Chapter Co-chair – Europe Ionescu Chapter Co-chair – Korea ERD Chung Memory Zhirnov Logic Bourianoff More-than-Moore Brillouet Architecture Franzon Editorial Team Hutchby, Bourianoff, Brillouet, Franzon, Chung, Garner/Herr, Ionescu, Zhirnov, Uchida ITRS Liaisons PIDS Ng, Hutchby FEP Colombo Modeling & Simulation Das/Shankar Materials Garner Metrology Herr/Obeng Design Yeh/Bourianoff More than Moore Brillouet 2011 ERD Working Group Organization

8. ERD Chapter due August 15, 2011 Major Tasks and Time Line Scope, Difficult Challenges, etc. April 30 Outlines for Memory, Logic, MtM, Arch, Mat’l April 30 Technology Requirements Tables July 1 Tables sent to editor August 1 Guiding Principles Section April 30 Draft Text Completed Memory, Logic, MtM, Architecture, Material June 1 Benchmarking and Critical Review July 1 Chapter Completed Aug. 15 Chapter Frozen Sept. 15 Major Face-to-Face Meetings in 2011 ITRS/ERD Meeting Berlin, Germany April 10 ITRS/ERD Meeting at Semicon West (SF, CA) July 10 ITRS/ERD Meeting near Seoul, Korea Dec. 11 2011 ITRS/ERD Major Deliverables and Timeline

9. ERD Chapter due August 1 15, 2011 Major Tasks and Time Line Scope, Difficult Challenges, etc. April 30 Outlines for Memory, Logic, MtM, Arch, Mat’l April 30 Technology Requirements Tables July 1 DraftTables sent to editor August 1 June 1 Guiding Principles Section April 30 Draft Text Completed Memory, Logic, MtM, Architecture, Material June 1 Benchmarking and Critical Review July 1 Chapter Completed Aug. 15 Aug. 1 Chapter Frozen Sept. 15 Major Face-to-Face Meetings in 2011 ITRS/ERD Meeting P, Germany April 10 ITRS/ERD Meeting at Semicon West (SF, CA) July 10 ITRS/ERD Meeting near Seoul, Korea Dec. 11 2011 ITRS/ERD Major Deliverables and Timeline

13. Feedback on 2009 ERD Chapter Overall Comments • Excellent overall readability and balance as a summary • Appropriate level of detail • Scope • Define the terrain covered by performance gains • Define “ultimately scaled CMOS” • Clarify “new information processing paradigm” • Clarify “bulk CMOS” • Difficult Challenges • Clarify the term “bridge a knowledge gap” • Italicize “This development would provide a significant increase in information …” • Give an example of a new application that can be better performed by a new device than by CMOS. • Taxonomy – How useful is this to the reader? • Critical Assessment • Some editorial comments • Define “functional” • Is the term “access resistance” sufficiently general? • Comment on “compared to the existing memory technology” Should it say “compared to existing memory technology scaled to its limit:”? • How can we obtain more votes in the Critical Review? • Include the OPA score in the left column of ERD 14 and 15.

14. Feedback on 2007 ERD Chapter Overall Comments (Held over) • Mission of ERD is not clear cut to universities – clearly state the mission in the introduction. • Need more detailed discussion of key messages and issues between ERD and ERM • Is a Technology Entry being limited by Fundamental Limits or a technologically limited research gap? • ERD needs to maintain a dialog with the Systems Drivers Chapter • Should ERD continue to include a failing Technology Entry?

15. Feedback on 2009 ERD ChapterEmerging Research Memory Devices • Transfers • Expand the scope by including a new section on the “Select Device”, either a diode or transistor • Expand the scope by including Storage Class Memorysuch as Magnetic Packet Memory ( Racetrack) • Move Nanowire Phase Change Memory to the Memory Transition Table and recommend its transition to PIDS as a variant of PCM. • For the time being, keep the Electronics Effects Memory intact as a category for further discussion, with the exception of moving Fe Polarization Memory to the FeFET category and devising a new name to distinguish this from the Fe Capacitor Memory • Add a row in the Memory Table to include an indication of a particular memory suitability for SCM • Other comments • Include optical memory for More-than-Moore? • Need to define (or make a table) a role ( necessary condition) of memory element as an interconnection. Examples ; • For configurable logic using such as CMOL • For Inference Architecture such as Bayesian inference networks

16. Feedback on 2009 ERD ChapterEmerging Research Logic Devices (1/3) • Transfers • III-V Alternate Channel Materials to PIDS/FEP and • Low Dimensional Materials to PIDS/FEP (keep GNR & CNT FETs) • Move Molecular Devices to the Transition Table. • Include Band-to-Band Tunneling Device category in Table 1. • Move RTD out of Table 2 to Transition Table • Other comments (decisions) • Keep the 3 Logic Tables used in 2009 and change “Channel” to “Device” in the first table. • Keep open for more discussion the disposition of vertical MOSFETs – Decide in Dec. Meeting • Put the Tunnel Transistor in the Transition Table for Logic • Add a new Section on More-than-Moore focused on Wireless Devices. • Move the SET to the new More than Moore Section • Move the Negative Capacitive Devices to the Logic Transition Table

17. Feedback on 2009 ERD ChapterEmerging Research Logic Devices (2/3) • Other comments (decisions) • Include the “Mott FET’ in the Logic Tables. (Call it Electronic Phase Change?) • Mention “Excitonic Device” in the Logic Text – put in the Logic Transition Table? • Under Collective Spin Devices include: Spin Wave Device and All Spin Logic • The IRC approved the ERD and ERM to publish the results of the Barza Memory Workshop, but make clear that this is not a selection of a technology • Transfer unconventional FET s, Tri-Gate, FinFET, GAA FETs, to PIDS/FEP • Other comments (under discussion) • In the Logic Transition Table, the IN/OUT entries for Ge FET, Spin MOSFET, Collective Spin Devices, Pseudomorphic, and Nanomagnetic Devices should be move into the Comment column to the right. Entries in the IN/OUT column might better be technical in nature.

18. Feedback on 2009 ERD ChapterEmerging Research Logic Devices (3/3) • Other comments (under discussion) • Introduction of energy efficiency criteria? Important • Role of other functionality than digital of beyond CMOS: image processing, analog, RF, etc. • Convergence of beyond CMOS and More than Moore technology entries? MEMS/NEMS already in chapter. • More interaction with emerging architectures needed.

19. Backup Slides

20. A Taxonomy for Nano Information Processing Technologies Conventional Scaled CMOS Architecture Reconfigurable Morphic Analog Quantum Von Neumann Data Representation Analog Digital Patterns Quantum state New Information Processing Technologies Device Spintronics Quantum SETs Molecular Ferromagnetic Scaled CMOS Material Carbon Strongly correlated mat’ls Silicon Ge & III-V mat’ls Nanostructured mat’ls State Variable Spin orientation Molecular state Electric charge Phase state Strongly correlated electron state

21. 2009 ITRSEmerging Research DevicesEditorial – Driver Team MeetingCharter and Scope George Bourianoff Mike Garner Jim Hutchby Victor Zhirnov Santa Clara, CA October 13, 2004 Edited December 10, 2006

22. On behalf of the 2011 ITRS, develop an Emerging Research Devices chapter to -- Critically assess new approaches to Information Processing technology beyond ultimate CMOS Identify most promising approach(es) to Information Processing technology to be implemented by 2026 To offer substantive guidance to – Global research community Relevant government agencies Technology managers Suppliers Charter of ERD Chapter

23. Integrated emerging research memory, logic and new architecture technologies enabled by supporting -- Materials and process technologies Modeling and simulation Metrologies Selection of specific technical approaches shall be Guided by fundamental requirements Bounded by ERD’s topic selection criteria Scope of ERD Chapter

24. Devices and Architectures – Published by 2 or more groups in archival literature and peer reviewed conferences, or Published extensively by 1 group in archival literature and peer reviewed conferences Technology Entry (by itself or integrated with CMOS) must address a major electronics market. Materials and Fabrication Technologies – Materials and processes that address the specific material needs defined by emerging research device technology entries Supporting disciplines – specify for crosscut TWGs Metrologies Modeling & simulation Scope of ERD ChapterCriteria for Including Technology Entries

25. Decisions for 2009 Chapter Fig. 4

26. Decisions for 2009 Chapter Fig. 5

27. Decisions for 2009 Chapter Fig. 6

28. Decisions for 2009 Chapter (Divide into 3 tables to match the three logic tables) Fig. 7

29. Decisions for 2009 Chapter Fig. 8

30. Computational state variable(s) other than solely electron charge. These include spin, phase, multipole orientation, mechanical position, polarity, orbital symmetry, magnetic flux quanta, molecular configuration and other quantum states. Non-thermal equilibrium systems to reduce the perturbations of the stored information energy by thermal interactions with the environment (e.g., systems that perform all processing functions in a time short compared to the system’s energy relaxation time to improve thermal noise immunity). Nanoscale thermal management. This might be accomplished by manipulating lattice phonons for constructive energy transport and heat removal. Novel information transfer mechanisms. These mechanisms would provide the interconnect function between communicating information processing elements, and input/output. Alternative Architectures. In this case, architecture is the functional arrangement on a single chip of interconnected devices that includes embedded computational components. These architectures should utilize, for special purposes, novel devices other than CMOS to perform unique functions. Sub-lithographic manufacturing process (e.g., directed self-assembly of complex structures composed of nanoscale building blocks) The approaches should address essential non-regular, hierarchically organized structures, be tied to specific device ideas, and be consistent with high volume manufacturing processes. “Guiding Principles”