Actuation Electronics For (Near) Future Detectors

1. Actuation Electronics For (Near) Future Detectors Alberto Gennai alberto.gennai@pi.infn.it

2. Introduction • The VIRGO Suspensions are complex mechanical structures used to insulate optical elements from seismic noise. The structure, described by an 80 vibrational modes model, is controlled by 18 coil-magnet pairs commanded with two distinct Digital Signal Processors operating at 10 kHz sampling frequency. The suspension status is observed using 20 local sensors plus optional 3 global sensors. • The new control system foresees multi-DSP computing units, faster and higher resolution analog-to-digital and digital-to-analog converters and high dynamic power driver for coil-magnet pair actuators. A.Gennai (INFN Pisa)

3. Last Stage Actuators • Last stage actuators play a fundamental role applying forces directly on test masses. • This talk concentrates on two key aspects of actuators electronics: • Dynamical range • Electro-Magnetic Immunity A.Gennai (INFN Pisa)

4. VIRGO Suspension Control Unit • 2 x Motorola PowerPC-based CPU boards • 2 x Motorola DSP96002-based boards • 60 Analog I/O channels • 4 Digital optical point-to-point links (LAPP Annecy) • CCD Camera Interface (LAPP Annecy) • 10 kHz Sampling • 16 (14.5 eff.) bits ADC • 20 (17.5 eff.) bits DAC • About 100 poles for each DSP A.Gennai (INFN Pisa)

5. Actuators Electronics Dynamical Range • Power amplifiers used to drive coil-magnet pair actuators steering VIRGO optical elements need a wide dynamical range: • Big force impulse required for acquiring the lock of VIRGO optical cavities • Low noise during linear regime. • The rms value of correction signal decreases while sensitivity approaches VIRGO goal curve: • Need of a flexible solution able to easily adapt to sensitivity changes without limiting control signal dynamics A.Gennai (INFN Pisa)

6. The use of a Digital to Analog converter to drive actuators electronics limits the actuator dynamic. • At present in VIRGO we use 20 bit DAC • Vmax = 10 V • Vnoise = 300 nV/Hz1/2 • New VIRGO coil driver shall supply • Imax = 2 A • Inoise = 3 pA/Hz1/2 A.Gennai (INFN Pisa)

7. New Coil Drivers • A new coil driver was designed using two distinct sections: • high power section for lock acquisition • low noise section for linear regime. • The two sections are driven by two independent digital-to-analog converter channels. A.Gennai (INFN Pisa)

8. New Coil Driver: Basic Operation • Dynamical range extension is obtained using two DAC channels. • DAC #1 is used during lock acquisition phase (2A current). During this phase DAC #2 is set to zero. • DAC #1 is then set to zero and simultaneously DAC #2 is activated • High power section is disconnected from coil actuator A.Gennai (INFN Pisa)

9. DAC Noise Contribution Simulated data A.Gennai (INFN Pisa)

10. New Coil Driver: Block Diagram • For each actuator three distinct section are available (one High Power plus two Low Noise). • The High Power section is a transconductive amplifier able to supply up to 2 A into the coil while the two Low Noise sections are voltage amplifiers with series resistor • The three sections architecture will allow switching from lock acquisition to linear lock regime in two (or more) steps.

11. Prototype (installed at terminal towers)

12. Experimental Results Bad EMI due to bad PCB A.Gennai (INFN Pisa)

13. Electro-Magnetic Immunity • Power Supply • Only linear power supply is allowed. Supply shall be separated from analog circuits. A star grounding scheme shall be adopted. • PCB • Multi-layer circuit boards with signal lines sandwiched between ground planes. • … • Circuits Shielding • Analog and digital circuits shall be separated with independent Faraday shielding. • Shielded crates shall be utilized • External Wiring A.Gennai (INFN Pisa)

14. EMI – External Wiring • Each coil driver is connected via a 30 meters long Shielded Twisted Pair (STP) cable to the digital to analog converter (DAC) board. • To improve EMI/EMC, digital to analog and analog to digital converters, shall be made available on-board. • Processing nodes shall be connected to front end electronics using galvanically isolated wiring with optical or RF couplers A.Gennai (INFN Pisa)

15. High Power Coil Current Monitor ADC DAC DAC Low Noise Coil Current Monitor ADC Low Noise Section #2 Low Noise Section #1 High Power Section Digital IN Digital OUT Digital IF Coil Control Section Serial Link Coil Drivers: Digital I/O 10 Mb/sec digital data electrically isolated • Sections switch • Gain selection • De-enphasis filtering • Monitor configuration A.Gennai (INFN Pisa)

16. Digital I/O • Several devices shall be connected to the same serial line therefore selected communication protocol shall support multipoint (multiplex) transmission mode where multiple transmitters and receivers share the same line. • A single fiber optic link shall provide the connectivity between front end electronics and processing nodes. • IEEE 1394b-2002 standard will be adopted for physical layer A.Gennai (INFN Pisa)

17. Facing “Control Noise” • In addition to standard noise sources, a new contribution, referred as “Control Noise”, is becoming more and more relevant • Control noise is the noise injected into the system by non optimal design of control algorithms often due to limited online computing resources • To face this problem we decided to drastically increase the computation power of processing units A.Gennai (INFN Pisa)

18. Multiprocessor DSP Board: Main Features • 6 x 100 MHz ADSP211160N SHARC DSP • 3.4 GigaFLOPS • 1800 MB/s of low latency inter processor communication bandwidth • 512 MB SDRAM • 64-bit 66 MHz PCI bus • On board 32-bit Master-Slave PCI to DSP Local Bus bridge • 256 kWord real Dual Port memory (PCI – DSP LB) • VME to PCI Master – Slave bridge • DSP LB to VSB bridge for I/O devices access • 200 MB/s auxiliary I/O bandwidth • 2 x Altera EP1C4 Cyclone FPGA • Compact size: PMC standard (149 x 74 mm) A.Gennai (INFN Pisa)

19. Dual Port Memory M A 4 3 2 5 6 1 B DSP FPGA MDSPAS – Top View A.Gennai (INFN Pisa)

20. PCI 64 – 66 MHz SDRAM I/O  TimDOL VSBbus MDSPAS – Bottom View A.Gennai (INFN Pisa)

21. How use 3.2 GFLOPS? • Digital Feedback Design in VIRGO • Usual specifications: “Use high loop gain over some frequency range then decrease the gain as rapidly as possible” • Classical Design Methods (SISO) • Discrete-time controllers derived from continuous-time controllers (indirect design techniques) • Design a continuous-time controller and then obtain the corresponding discrete-time controller using a transformation from G(s) to G(z). A.Gennai (INFN Pisa)

22. Feedback Design Methods • Classical Design Methods (SISO) • Root locus method • Nyquist techniques (design based on frequency response) • PID Controller design methods • Transient response method • Stability limit method • State Space Design Methods (SISO – MIMO) • Pole Placement • Optimal Control - LQG Methods • H-Infinity • ... • Adaptive Control • Model Reference adaptive control • Self-tuning regulators • … Additional computational power will allow implementing MIMO and adaptive controllers, with major advantages from the so called “control noise” point of view A.Gennai (INFN Pisa)

23. Conclusions • Improving VIRGO sensitivity at low frequency requires huge dynamical range actuators electronics • Dynamical range can be improved using different hardware configurations for lock acquisition and linear lock phases • A good “stand-alone” device can easily become a bad one once installed. Special care shall be devoted to devices interconnections and EMI • Use of “clever” control algorithm A.Gennai (INFN Pisa)