Adiabatic Logic as Low-Power Design Technique

Adiabatic Logic as Low-Power Design Technique Presented by: Muaayad Al-Mosawy Presented to: Dr. Maitham Shams Mar. 02, 2005

Project Objective Motivation for Low-Power Power Consumption in CMOS Circuits Low-Power Design Techniques Adiabatic Logic Adiabatic Charging Principle Adiabatic Recovery Requirements Adiabatic Logic Families Complementary Pass-Transistor Energy Recovery Adiabatic Logic (CPERL) Time Table References Contents M. Al-Mosawy

Project Objective • Investigating a type of adiabatic logic called Complementary Pass-Transistor Energy Recovery Logic (CPERL) • Based on this logic, a chain of inverters will be implemented to compare the the power dissipation with a similar chain of conventional inverters • 16 bit brent-kung CPERL adder will be designed to verify the target logic M. Al-Mosawy

Motivation for Low-Power - 1 • Long life batteries operations • Complexity increases, energy budget remains same • Complex high speed devices: - Thermal problems - Expensive packaging • Weight, size and cost reductions • Noise immunity M. Al-Mosawy

Motivation for Low-Power - 2 M. Al-Mosawy

Motivation for Low-Power - 3 M. Al-Mosawy

Power Consumption in CMOS Circuits - 1 • Power dissipation in a typical CMOS circuit can be:  Dynamic Power dissipation (Pdyn): - Switching Power (Pswitch) - Short circuit power (Psc)  Static power dissipation (Pstatic): - DC power (Pdc) - Leakage power (Pleakage) M. Al-Mosawy

Power Consumption in CMOS Circuits - 2 M. Al-Mosawy

Low-Power Design Techniques M. Al-Mosawy

Adiabatic Logic - 1 • Adiabatic means: of, relating to, or being a reversible thermodynamic process that occurs without gain or loss of heat • In ideal adiabatic logic, each charge could be recycled (reused) an infinite number of times • Practically, this is not possible • By adopting a real adiabatic logic, each charge can be recycled for many time so that a significant power dissipation reduction would be possible M. Al-Mosawy

Adiabatic Logic - 2 • To achieve the charge saving expected from adiabatic logic, one of two power supplies is to be used: - Constant current power supply - Variable voltage supply M. Al-Mosawy

Adiabatic Charging Principle • Energy can be traded for delay by increasing the charge transport time M. Al-Mosawy

Adiabatic Recovery Requirements • In general, in order to restore the charge, three principles should be followed by any MOS devices in an adiabatic circuit: - A device can be turn on only while the source-drain voltage is zero - Source-drain voltage can be changed only while the device is off - Any voltage change must be done gradually M. Al-Mosawy

Adiabatic Logic Families • Partially adiabatic circuits • Some energy is recovered  2N2P / 2N-2N2P  CAL (Clocked CMOS Adiabatic Logic)  TSEL (True Single Phase Adiabatic)  SCAL (Source-coupled Adiabatic Logic) • Fully adiabatic circuits • Dissipate little energy, very slow  PAL (Pass-transistor Adiabatic Logic)  Split-level Charge Recovery Logic (SCRL) M. Al-Mosawy

Complementary Pass-Transistor Energy Recovery Adiabatic Logic (CPERL) - 1 • The figure shows a CPERL inverter • All devices are NMOS • The gate consists of two parts - Charge/discharge function part (M1 – M6) - Logic function part (M9 – M10) • Different logics can be achieved by changing the logic function part with a different logic tree M. Al-Mosawy

Complementary Pass-Transistor Energy Recovery Adiabatic Logic (CPERL) - 2 M. Al-Mosawy

Complementary Pass-Transistor Energy Recovery Adiabatic Logic (CPERL) - 3 • An assumption was made that 1 and IN are in the same phase • As 1 ramps up, IN rises also • Inbar remains low • M9 & M11 turns on • BN1 is precharged to (Vdd – Vth) • BN2 is still at low voltage M. Al-Mosawy

Complementary Pass-Transistor Energy Recovery Adiabatic Logic (CPERL) - 4 • When 1 ramps down, IN goes down also causing M9 & M11 to turn off • As 2 ramps up and due to the gate-to-channel capacitance in M1, BN1 goes higher than Vdd causing M1 to turn on • 2 will charge the node OUT in an adiabatic manner to Vdd • As 2 ramps down, OUT goes down also • The charge stored on OUT is recovered to supplied through the discharge process M. Al-Mosawy

Complementary Pass-Transistor Energy Recovery Adiabatic Logic (CPERL) - 5 • Two stages of CPERL inverters chain are shown and just half of the circuit for the simplicity • During period t1, A is assumed high and BN2 is at (Vdd-Vth) • During t2, 2 ramps downand the the charge will trapped at BN2 • During t3, 2 rises again • Assuming that Ais Low and Abar is high, M10 of stage 2will turn on M. Al-Mosawy

Complementary Pass-Transistor Energy Recovery Adiabatic Logic (CPERL) - 6 • M3 of stage 1 will turn on also • Current will flow through M10 & M3due to voltage difference • This charge sharing will stop when a voltage balance occurs between the nodes • M5 is working under diode connection • If the voltage difference is still higher than Vth, M5 will turn on until the voltage difference becomes lower than Vth • If this difference is already less than Vth, M5 will stay off M. Al-Mosawy

Complementary Pass-Transistor Energy Recovery Adiabatic Logic (CPERL) - 7 • Brent Kung adder has three units: - Propagate and generate unit - Carry parallel prefix unit - The sum unit M. Al-Mosawy

Time Table* M. Al-Mosawy

References • R. C. Chang, P. C. Hung and I.-H. wang, “Complementary pass-transistor energy recovery logic for low-power applications”, IEEE Proc.-Comput. Digit., Tech., Vol. 149, No. 4, July 2002 • Chulwoo Kim, Seung-Moon Yooand Sung-Mo, “Low-power computing with NMOS energy recovery logic”, IEEE, Electronic letters, Vol. 36, No. 16, Aug. 2000 • J. Rabaey, A. Chandrakasan and B. Nikolic, “Digital Integrated Circuits”, Prentic Hall, 2003 • M. Khellah, “Low-Power Digital CMOS VLSI Circuits and Design Methodologies”, U. of Waterloo, 1999 • V. Kottamasu , “Study and Comparison of a 0.18micron technology 8 bit Brent-Kung adder “, www.iit.edu/~kottven/research.htm M. Al-Mosawy

Adiabatic Logic as Low-Power Design Technique