A General Purpose Charge Readout Chip for TPC Applications Munich, 19 October 2006 Luciano Musa

1. A General Purpose Charge Readout Chip for TPC Applications Munich, 19 October 2006 Luciano Musa Gerd Trampitsch

2. OUTLINE • R&D on the readout electronics for the LC TPC • Alice TPC Readout - MWPC • General Purpose Charge Readout Chip • Prototype Submission of the Analog Front End • Multi Rate ADC • Project Milestones • Next Steps

3. Digital Circuit Alice TPC – MWPC Readout Front End Electronics Architecture FEC (Front End Card) - 128 CHANNELS (CLOSE TO THE READOUT PLANE) DETECTOR Power consumption: < 40 mW / channel L1: 5ms 200 Hz 8 CHIPS x 16 CH / CHIP 8 CHIPS x 16 CH / CHIP drift region 88ms L2: < 100 ms 200 Hz ALTRO gating grid PASA ADC RAM anode wire DDL (3200 CH / DDL) CUSTOM IC (CMOS 0.35mm) pad plane 570132 PADS CUSTOM IC (CMOS 0.25mm ) CSA SEMI-GAUSS. SHAPER 1 MIP = 4.8 fC S/N = 30 : 1 DYNAMIC = 30 MIP • BASELINE CORR. • TAIL CANCELL. • ZERO SUPPR. 10 BIT < 10 MHz MULTI-EVENT MEMORY GAIN = 12 mV / fC FWHM = 190 ns

4. 17 cm 19 cm ALICE TPC Front End Card Integrated charge amplification, digitization and signal preprocessing in the TPC end plate 128 channels

5. Requirements of the front-end and readout electronics for High Energy Physics Experiments: low power, high speed, high density, low mass, radiation tolerance These requirements can only be met by highly integrated systems implemented with very deep submicron CMOS technologies. The volumes of ICs required for a typical HEP detector remain low <1Mch Non Recursive Engineering (NRE) costs are more and more dominant for high energy physics. Development of standard chips capable of handling a wide range of high energy physics applications, in order to warrant the NRE expenditure. Likely this polyvalence will be obtained through an increased level of programmability. Motivations & Specifications 1/2

6. A general purpose charge readout chip number of channels: 32 or 64 programmable charge amplifier: sensitive to a charge in the range: ~102- ~107 electrons Input capacitance: 0.1pF to 10pF Peaking time: 20ns – 100ns high-speed high-resolution A/D converter: sampling rate in the range 40MHz - 160MHz; programmable digital filter for noise reduction and signal interpolation; a signal processor for the extraction and compression of the signal information (charge and time of occurrence). Motivations & Specifications 2/2

7. Charge Readout Chip Block Diagram Anti-Aliasing Filter Anti-Aliasing Filter Anti-Aliasing Filter Signal Processor Signal Processor Signal Processor Data Compression Data Compression Data Compression Multi-Acq Memory Multi-Acq Memory Multi-Acq Memory Charge Amplifier Charge Amplifier Charge Amplifier ADC ADC ADC I N T E R F A C E Hit Finder • Maximize S/N • reduce quantization error • reduce signal bandwidth • Correct for crosstalk and common mode noise • Optimum pulse shaping for extraction of pulse features Feature Extaction Histogrammer 32 / 64 Channel

8. Milestone I (Q1 2007) ⇒ Programmable Charge Amplifier (prototype) 16 channel charge amplifier + anti-aliasing filter Milestone II (Q2 2007) ⇒ 10-bit multi-rate ADC (prototype) 4-channel 10-bit 40-MHz ADC. The circuit can be operated as a 4-channel 40-MHz ADC or single-channel 160-MHz ADC Milestone III (Q2 2008) ⇒ Charge Readout Chip (prototype) This circuit incorporates 32 (or 64) channels. Milestone IV (Q2 2009) ⇒ Charge Readout Chip (final version) Project Milestones

9. Low-noise Amplifier (CMOS 0.13mm) Improved ENC • Increased gm (Ideally approx. 20% per CMOS Generation) • Low Supply Voltage limits SNR • Smaller Dynamic Range • Rail to Rail Design • Invest Power to improve SNR • Big Capacitors • Design Shaping Circuit for Low Noise • Reduced Gate Oxide Thickness • Gate Tunneling Current • Radiation Tolerance • Short Channel Effects • Hot Carrier Stress – Reliability, Noise • Velocity Saturation

10. Prototype Architecture H(s) H(s) H(s) • PASA – Channel Architecture • Single Ended Charge Sensitive Preamplifier • Nonlinear Pole Zero Cancellation • 2 Shaping Amplifiers • Fully differential Rail to Rail Output Amplifier • Driving Capability of 30 pF • Optimized for one Signal Polarity

11. 5 versions 7 standard channels Programmable Charge Amplifier Gerd Trampitsch INPUTS Production Engineering Data • 12- channel 4th order CSA • various architectures (classical folded cascode, novel rail-to-rail amplifier) • process: IBM CMOS 0.13 mm • area: 3 mm2 • 1.5 V single supply • Package: CQFP 144 • MPR samples (40): Apr ‘06 single channel OUTPUTS

12. Programmable Charge Amplifier • The CQFP 144 package has the same pin-count and similar pinout as the ALICE TPC PASA • In the near future the new chip will be tested on a ALICE TPC FEC Next Step • Milestone I (Q1 2007) ⇒ Programmable Charge Amplifier (prototype) • 16 channel charge amplifier + anti-aliasing filter • Programmable gain and peaking time (20ns – 100ns) • Both signal polarities • Design is in progress • Submission in Q1 2007

13. Pipelined ADC – 40 MHz • ALTRO – Pipelined ADC • Designed in 0.25 μm process • Design transferred to 0.13 μm – Upgrade of ALTRO ADC

14. up Phase Detector Charge Pump down Ref. Clock (40 MHz) Vctrl Voltage Controlled Delay Line CLK CLK A A A A fa fa A fb 4-Channel 40-MHZ ADC B fb fc A A B B fc CLK fd 2-Channel 80-MHZ ADC A fd fa C fb C A C C fc A 1-Channel 160-MHZ ADC C fd D C D A D Multi-Channel Time-InterleavedA/D Converter Upgrade of ALTRO ADC A/D A/D A/D A/D A/D

15. The development of a general purpose charge readout chip has started. This chip incorporates: Programmable analogue front end Multi-rate Analogue to Digital Converter General purpose signal processor First prototype of the shaping amplifier in CMOS 0.13 μm Submitted in December 2005 40 samples of the MPWR successfully characterized in 2006 All circuit parameters meet the design specifications The design and layout of a programmable gain and bandwidth amplifier is currently in progress and will be finished early next year Time interleaved Multi-Rate ADC The basic building block was transferred to IBM 0.13 μm Design is still in progress Summary