Hybrid Conditional Sum/Carry Lookahead Adder.

1. Hybrid Conditional Sum/Carry Lookahead Adder. by Stephen Malchi

2. Project objective • To design a low power high performance adder • Sub micron technology • Power is the main concern

3. Conditional Sum Adder • Generates individual sum and carry bits. • Selects the true output based on the carry of previous stage.

4. 8-bit CSA Block diagram

5. Hybrid CS/CLA

6. Theoretical Delay • Conditional Sum Adder T = (log2n +1).2∆ = 18∆ • Hybrid Adder producing g’s and p’s 1∆ producing internal carries 2∆ 3 ∆ * 4 = 12 ∆

7. Design • Verilog gate level simulated and verified for functionality using Modelsim.

8. Static CMOS CPL (Complementary Pass Transistor Logic) Most efficient pass transistor logic Small input load and good output driving capability Reto Zimmermann and wolfgang Fichtner, Low- Power Logic Styles: CMOS versus Pass-Transistor Logic Design Styles

9. CPL gates

10. Adder Adder Power (mW) Power (mW) Delay (ps) Delay (ns) CSA CSA 2.80 6.34 714 1.2 HCSA HCSA 1.65 5.65 0.676 349 CCA CCA 1.78 5.25 648 1.02 HCCA HCCA 1.56 4.83 0.632 348 Simulation Result Static CPL

11. Conclusion • Hybrid Adder performance is better • The advantages of CPL are restricted by the swing restoration circuitry • Static is a better choice than CPL. • Conditional Carry adder • Reduces the MUX count by half in turn saves power and increases speed.

12. References • [1] Behrooz Parhami – Computer Arithmetic Algorithms and Hardware Designs. • [2] Kuo-Hsing Cheng, Shu-Min Chiang and Shun –Wen Cheng – The Improvement of Conditional Sum Adder for Lower Power Applications. • [3] J.Slansky, Conditional Sum Addition logic. IRE Trans. Electron Computer. VOL EC-9 (1960).

13. References cont. • [4] Reto Zimmermann and wolfgang Fichtner, Low- Power Logic Styles: CMOS versus Pass-Transistor Logic.