Temperature, Voltage and Process Variations in SRAMs

1. Temperature, Voltage and Process Variations in SRAMs • Shrikanth Ganapathy1, Ramon Canal1, Antonio Rubio1, Antonio Gonzalez 1,2 • 1Universitat Politecnica de Catalunya, Spain • 2Intel Barcelona Research Center, Spain CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011

2. Variation in 6T based Memories CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011 • Withreduction in feature sizes, Memory systems will be affected the most. • Intrinsic device level fluctuations will dominate over other forms of variations. • Reduction in size means smallerQcrit, making it more susceptible to Hard Errors. • Controlling the intrinsic fluctuations is beyond the capabilities of Manufacturing processes. • In addition to Memory Cells, Peripheral Circuitry which make up the entire system will also be severely affected. • Besides Energy, the parameter of Delay would become one of the most important design constraints. • Difference in parameter values at design time and obtained chip constitute Spatial variability • Arise out of Process Tolerance • Affect Physical parameter Values within and across dies. • Rapid changes in environmental & operating conditions create heterogeneous conditions across time (Temporal Variability)

3. Sources of Variability T T T Vth Leff Vth T Vth T Leff Vth T Vth T Parameters Affected Leff T - Temperature Vth - Threshold Vth Leff Leff - Effective Length CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011

4. Estimating Spatial Variations • Multilevel Quad-tree based partitioning • For each level n, the die is partitioned into 2nx2n squares. • The top most level represents the entire die • Similar Layout structures in a given grid are grouped in the same grid above the current grid Inter Die Intra-Die (Systematic) Intra-Die (Random) P = Pnominal+ ∆Inter-Die + ∆ Intra-Die CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011

5. Delay Variability • Generational reduction in threshold, widens the gap in access time as temperature increases. • For worst case temperature, under process variations, the access time deviation between best and worst performing chip is around 50% prompting the need for aggressive remedial solutions. Zero Spatial Variation CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011

6. Energy Variability • The potential benefits of supply voltage scaling are large provided energy-delay tradeoffs are analyzed early. • While reducing supply reduces dynamic power, in sub-32m designs, temperature dependent leakage will be equal/higher when compared to dynamic power. CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011

7. Importance of Peripheral circuitry CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011 • Peripheral Circuitry form the core of the system. • Peripheral Circuitry Composed of : • Pre Decoder • Address Decoder • Column Multiplexers • Sense Amplifiers. • Structure with minimum number of Transistors driving large loads are most susceptible to variations .

8. Delay Modeling High dependence of delay on temperature translates to multiple PDFs as against single PDF suggested by SSTA techniques. As delay is linearly dependent on threshold, effective length, we begin with a first order polynomial and fit to the best curve. CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011

9. Energy Modeling The static and dynamic energy of every component in the array sub-block is estimated at different instants of time. Energy is estimated as a function of the integral of current through the supply (non-capacitive). In order to reduce the dimensions of the equations resulting from fitting using a first-order curve, we use main-effect analysis. CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011

10. Statistical Energy-Delay Optimization • Estimate Energy and Delay of every cache structure using circuit level simulation. • Using multivariate linear regression, fit input parameters to output curve. • Repeat process until, RMS is minimal. • While, threshold of memory array constant, change threshold of periphery in steps of 25mV. • Determine Energy and Delay simultaneously using fitted curves. • Reduce standby supply voltage of unaccessed block, to determine dynamic energy. • While delay within 10% of best delay, determine threshold for least energy. CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011

11. Access Time Reduction Post-Optimization CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011

12. Energy Reduction Post-Optimization Normalized Energy Standby Supply Voltage CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011

13. Conclusion • Execution times largely dominated by accesses to the cache will be severely hit due to parameter variations. • Multivariate regression provides means of estimating energy-delay simultaneously with very high speedups. • The generated models can then be used for post-simulation statistical circuit optimization. CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011

14. Thanks for your attention! CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011