Design of Regular Quantum Circuits

1. Design of Regular Quantum Circuits Regular circuit = tile-based circuit

2. REVERSIBLE LOGIC

3. Reversible Permutative logic Gates and Circuits • A logic gate is reversible if • Each input is mapped to a unique output • It permutes the set of input values • A combinational logic circuit is reversible if it satisfies the following: • Has only one Fanout, • Uses only reversible gates, • No feedback path, • has as many input wires as output wires, and permutes the input values.

4. Basic Reversible Gates NOT gate Controlled-NOT or Feynman gate a b a c 0 0 0 0 0 1 0 1 1 0 1 1 1 1 1 0

5. a b c a b f 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 1 1 1 1 1 1 0 Basic Reversible Gates Toffoli gate (Controlled-Controlled NOT gate)

6. Basic Reversible Gates Swap gate Implementation of Swap gate using controlled-NOT

7. a b c a f g 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 1 0 1 1 0 1 0 1 1 1 1 1 1 1 Basic Reversible Gates Fredkin gate (Controlled SWAP gate)

8. Algorithms for Synthesis of Reversible Logic Circuits

9. Popular Algorithms for Synthesis of Reversible Logic Circuits • MMD: Transformation based • Gupta-Agrawal-Jha: PPRM based • Mishchenko-Perkowski: Reversible wave cascade • Kerntopf: Heuristics based • Wille: BDD based synthesis

10. reed-mulLER EXPANSION IN SYNTHESIS OF REVERSIBLE CIRCUITS

11. IDEA: use reed-mulLER EXPANSION IN SYNTHESIS OF REVERSIBLE CIRCUITS A New Representation is Reed-Muller Expansion (Positive Polarity Reed-Muller). This idea appeared for the first time in paper of Aggrawal and Jha, this paper was a competitor to MMD algorithm. Now we design a new algorithm which takes into account multi-level expansion for reversible circuits.

12. Example of Agrawal-Jha Algorithm • PPRM form for each output in terms of • Input variables are given as follows and • node is created • Reversible function specification is given as a truth table shown here • Output c0, b0 and a0 are derived using EXORCISM-2 developed at PSU and parent node is created

13. Agrawal-Jha Algorithm (cont..) • Parent node is explored by examining each output variable in the PPRM expansion. • Factors are searched in the PPRM expansions that do not contain the same input variable. • For example in the expansion below appropriate terms are “c” and “ac” • The substitution is performed as • In this example OR

14. Agrawal-Jha Algorithm (cont..)

15. Agrawal-Jha Algorithm (cont..) New nodes are created based on substitution

16. Next stage of Aggrawal-Jha algorithm

17. Next stage of Aggrawal-Jha algorithm

18. Solution found by the Aggrawal-Jha algorithm

19. Problem with Current Synthesis Approaches • Common problem with current approaches: they invariably use nxnToffoli gates, that might imposes technological limitations. • High Quantum cost of Toffoli gates with many inputs. • Synthesize only reversible functions, not Boolean functions that is not reversible.

20. Quantum Cost of 4x4 Toffoli Gate • Implementation of 4x4 Toffoli gate with Quantum realizable 2x2 primitives such as controlled-V, controlled-NOT, controlled-V+.

21. CREATING QUANTUM ARRAY FROM LATTICE

22. Expansions Rules for Lattice DIAGRAAMS • Positive Davio Tree can be created by expanding PPRM function using positive Davio expansion. • Positive Davio Lattice is created by performing joining operation for neighboring cells at every level. • Other Lattices can be created using similar method but using expansions such as Shannon or Negative Davio expansions or combination of them.

23. Creating Quantum Array from Lattices • On the previous foils I showed representation of the Davio and Shannon cells as cascade of reversible gates. • Next I present unique method to create Quantum Array from Positive Davio Lattice. • The same approach can be used for other Lattices.

24. Creating Positive Davio Lattice • Each node represents pDv cell.

25. Creating Quantum Array from Positive Davio Lattice + c 1 + + 1 d d 1 + + 1 1 b b + + + 1 a 1 1 a 1 1 a 1 + 1 1 d 1 0 1

26. Å 1 a Å 1 ad Å Å 1 ab b Å Å Å Å Å b a d bd b abd a Å Å Å Å Å Å Å 1 db ad abd bc ac cd bcd Å Å Å 1 db abd ad Quantum Array Representation a b c d garbage d 0 garbage 1 garbage 1 garbage 1 garbage a 0 1 function

27. Å 1 a Å 1 ad Å Å 1 ab b Å Å Å Å Å b a d bd b abd a Å Å Å Å Å Å Å 1 db ad abd bc ac cd bcd Å Å Å 1 db abd ad Quantum Array Representation a b c d garbage d 0 garbage 1 garbage 1 garbage 1 garbage a 0 1 function

28. Creating Positive Davio Lattice • Each node represents pDv cell.

29. Quantum Array Representation

30. Advantages of Lattice to QA • Reversible circuit synthesized with only 3x3 Toffoli gates. • Generates reversible circuit for any ESOP. • Adds ancilla bits but overall cost of the circuit will be lower due to use of low cost 3x3 Toffoli gates.

31. Calculating Single-Output Shannon Lattice for Completely Specified Boolean Function.

32. Calculating Multi-Output Shannon Lattice for Completely Specified Boolean Function.

33. Calculating Multi-Output Shannon Lattice for Completely Specified Boolean Function.

34. DIPAL GATES, DIPAL GATE FAMILIES AND THEIR ARRAYS

35. Representation of pdv cell as a toffoli gate

36. Dipal cell representation with Shannon cell reversible gates a a a = Å f a b a c b = Å f a b a c b c Å c b c Development of Dipal gate • Dipal gate is a reversible • equivalent of Shannon cell • There are 23! = 8! = 40320 3x3 Reversible logic functions, however only handful of them shown earlier are useful for synthesis purpose. • Find the reversible counterpart of well-known structures BDD, Lattices, KFDD • Show Dipal cell is between Toffoli and Fredkin

37. Dipal cell with negative variable represented with Shannon cell with negative reversible gates variable a a a = Å b f a c a b Å b c b c = Å c f a c a b Development of Dipal gate (cont..)

38. Dipal cell representation with Shannon cell reversible gates a a a = Å f a b a c b = Å f a b a c b c Å c b c Development of Dipal gate • Dipal gate is a reversible • equivalent of Shannon cell • There are 23! = 8! = 40320 3x3 Reversible logic functions, however only handful of them shown earlier are useful for synthesis purpose.

39. Dipal gate truth table

40. Dipal gate unitary matrix 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111

41. Variants of Dipal gates This is called a Dipal Gate Family General view of Dipal Family Gate

42. EXPERIMENTAL RESULTS

43. Results with Pdv Lattice and comparison with MMD and AJ results

44. Results with Pdv Lattice and comparison with MMD and AJ results (cont..)

45. Results with shannon Lattice

46. Results with shannon Lattice (cont..)

49. Fig. 2. Circuit for function FX2 created with our method for traditional cost function calculation that does not take Ion Trap technology constraints into account.

50. Nearest Linear Node Model • Fig. 3. Circuit from Figure 2 modified with adding SWAP gates for new cost function calculation that does take Ion Trap technology constraints into account, with XX gates added. It has 36 SWAP gates added to realize LNNM. All gates are realized only on neighbors, but we have to add many SWAP gates