Processor Design

1. Processor Design Datapath and Design

2. All tables and diagrams in this presentation are from: D. Patterson and J. Hennessy, Computer Organization and Design: The Hardware/Software Interface, Third Edition (The Morgan Kaufmann Series in Computer Architecture and Design), Morgan Kaufmann, 2002.

3. Datapath

4. Basic Functional Units

5. Instruction Sequencing

6. Operations on Data in Registers

7. Registers and Memory

8. Simple Implementation Scheme Single cycle Implementation

9. ALU Conttrol

10. Control Signals

12. R-format and I-format Instructions

14. Control Signals and Instruction Opcode

16. Control Function

18. Multicycle Implementation

28. Intstruction fetch IR <= Memory[PC]; PC <= PC+4 IR <= Memory[PC]; PC <= PC+4

29. IorD= 0 MemRead= 1 IRWrite= 1 IR <= Memory[PC];

30. PCSource= 01 PCWrite= 1 ALUOp= 00 ALUSrcB= 01 ALUSrcA= 0 PC <= PC+4

31. Intstruction decode/register fetch A <= Reg[ IR [25:21]]; B <= Reg[ IR [20:16] ]; ALUOut <= PC + ( SignExt( IR[15:0] ) << 2 ) A <= Reg[ IR [25:21]]; B <= Reg[ IR [20:16] ]; ALUOut <= PC + ( SignExt( IR[15:0] ) << 2 )

32. A <= Reg[ IR [25:21]]; B <= Reg[ IR [20:16] ];

33. ALUOp = 00 ALUSrcB = 11 ALUSrcA = 0 ALUOut <= PC + ( SignExt( IR[15:0] ) << 2 )

35. R-type instruction ALUOut <= A op B Reg[ IR[15:11] ] <= ALUOut ALUOut <= A op B Reg[ IR[15:11] ] <= ALUOut

36. ALUOp = ?? ALUSrcB = 0 ALUSrcA = 1 ALUOut <= A op B

37. RegWrite = 1 MemtoReg = 0 RegDst = 1 Reg[ IR[15:11] ] <= ALUOut

39. Load instruction ALUOut <= A + SignExt(IR[15:0]) MDR <= Memory[ALUOUT] Reg[IR[20:16] ] <= MDR ALUOut <= A + SignExt(IR[15:0]) MDR <= Memory[ALUOUT] Reg[IR[20:16] ] <= MDR

40. ALUOp = 00 ALUSrcB = 10 ALUSrcA = 1 ALUOut <= A + SignExt(IR[15:0])

41. IorD =1 MemRead =1 RegWrite =1 MemtoReg =1 RegDst = 0 MDR <= Memory[ALUOUT] ; Reg[IR[20:16] ] <= MDR