DMA

1. DMA

2. canaux Deux blocs • EDMA_A 64 canaux (EDMA_A_BASE = 0xFFF44000) • EDMA_B 32 canaux (EDMA_B_BASE = 0xFFF54000) Le bloc A comporte 4 groupes: 0,1,2,3 Le bloc B comporte 2 groupes: 0,1 Chaque groupe a 16 canaux :0….15 Chaque canal dispose d’un TCD (transfert control descripteur)

3. Multiple loop iteration

4. Channel activation

5. Transfer examples

6. eDMA Block Diagram

7. Transfer Control descriptor (TCD) .

8. TCD structure

9. Struct tcd (.h) 1/2 • struct tcd_t { • vuint32_t SADDR; /* Source Address */ • vuint16_t SMOD:5; /* Source Address Modulo */ • vuint16_t SSIZE:3; /* Source Data Transfer Size */ • vuint16_t DMOD:5; /* Destination Address Modulo */ • vuint16_t DSIZE:3; /* Destination Data Transfer Size */ • vint16_t SOFF; /* Signed Source Address Offset */ • vuint32_t NBYTES; /* Inner ("Minor") Byte Transfer Count */ • vint32_t SLAST; /* Last Source Address Adjustment */ • vuint32_t DADDR; /* Destination Address */ • vuint16_t CITERE_LINK:1; /* Enable Channel-to-Channel */ • /* Linking on Minor Loop Completion */ • vuint16_t CITER:15; /* Current Major Iteration Count */ • vint16_t DOFF; /* Signed Destination Address Offset */

10. Struct tcd (.h) 2/2 • vint32_t DLAST_SGA; /* Last Destination Address Adjustment, or • Scatter/Gather Address (if E_SG = 1) */ • vuint16_t BITERE_LINK:1; /* Enable Channel-to-Channel */ • /* Linking on Minor Loop Complete */ • vuint16_t BITER:15; /* Starting ("Major") Iteration Count */ • vuint16_t BWC:2; /* Bandwidth Control */ • vuint16_t MAJORLINKCH:6; /* Link Channel Number */ • vuint16_t DONE:1; /* Channel Done */ • vuint16_t ACTIVE:1; vuint16_t MAJORE_LINK:1; /* Enable Channel-to-Channel Link*/ • vuint16_t E_SG:1; /* Enable Scatter/Gather Descriptor */ • vuint16_t D_REQ:1; /* Disable IPD_REQ When Done */ • vuint16_t INT_HALF:1; /* Interrupt on CITER = (BITER >> 1) */ • vuint16_t INT_MAJ:1; /* Interrupt on Major Loop Completion */ • vuint16_t START:1; /* Explicit Channel Start */ • } TCD[64]; /* Transfer_Control_Descriptor */ • };

11. (TCDn) SMOD/SSIZE/DMOD/DSIZE/SOFF

12. (TCDn) SMLOE/DMLOE/MLOFF/NBYTES

13. (TCDn) SLAST/DLAST_SGA

14. (TCDn) CITER.E_LINK/CITER.LINKCH

15. (TCDn) CITER/DOFF

16. (TCDn) BITER.E_LINK/BITER.LINKCH

17. (TCDn) BITER/BWC

18. (TCDn) MAJOR.LINKCH/DONE/ACTIVE

19. (TCDn) MAJORE.LINKCH/E_SG

20. (TCDn) D_REQ/INT_HALF

21. (TCDn) INT_MAJ/START

22. EDMA_A_CR

23. (EDMA_A_CR) CXFR/ECX

24. (EDMA_A_CR) GRPnPRI/EMLM

25. (EDMA_A_CR) CLM/HALT/HOE

26. (EDMA_A_CR) ERGA/ERCA/EDBG

27. EDMA_A_CR (.h) • union { /* Control Register */ • vuint32_t R; • struct { • vuint32_t:14; • vuint32_t CX:1; • vuint32_t ECX:1; • vuint32_t GRP3PRI:2; • vuint32_t GRP2PRI:2; • vuint32_t GRP1PRI:2; • vuint32_t GRP0PRI:2; • vuint32_t EMLM:1; • vuint32_t CLM:1; • vuint32_t HALT:1; • vuint32_t HOE:1; • vuint32_t ERGA:1; • vuint32_t ERCA:1; • vuint32_t EDBG:1; • vuint32_t:1; • } B; • } CR;

28. DMA initialzation Remarque: au reset les TCD ne sont pas resettès, donc initialiser tous les champs non utilisés

29. TCDn status bits

30. Single tranfer example

31. Example execution