Hardware/Software Codesign For Communication

1. Hardware/Software Codesign For Communication 설계자동화 연구실

2. 1. Hardware/Software Codesign • Integrated design of systems implemented using both hardware and software component. • Why? – Advances in enabling technologies: system level specification/simulation. high-level synthesis, CAD frameworks. – The increased diversity and complexity: advanced design methods required. – Cost and Performance of HW/SW system: to be optimized for market competitiveness. – Time to Market.

3. 2. Hardware/Software codesign의 목적 • Tolook for the best trade-off between Hardware and Software. • Needs for global system approaches that handle both complex behavior and high-level system. • The re-use of existing communication models in order to allow hardware/software synthesis and mapping on existing architecture platforms. • The increase of system production to use design automation technique.

4. 3. Hardware/Software codesign for Digital Communication Processing 1. Hardware/Software Codesign System Different steps of transformation • First step: Translating the application specification into the internal intermediate representation graph. • Second step: The analysis of the graph partitioning aspects performed by graph timing analysis. • Third step: The translation of the different level processing into the corresponding hardware orsoftware implementation

5. 3. Hardware/Software codesign for Digital Communication Processing Hardware/Software codesign system

6. 3. Hardware/Software codesign for Digital Communication Processing 1.1 Protocol Specification A dedicated programming language can be used to describe the protocol application for hardware/software codesign. 1.2 Protocol Implementation • System level Implementation – real-time processing layer: this layer deals with the treatment of the different bits of the basic message fields.

7. 3. Hardware/Software codesign for Digital Communication Processing – deferred real-time processing layer: the field sequencing of a message are considered in the second layer. Here are performed the field sequencing check and the field value validation. – deferred processing layer: higher level protocol processing are performed in this layer. The different associated functionalities are concerned with the message processing like sequencing, checking, connection management,…

8. 3. Hardware/Software codesign for Digital Communication Processing System level implementation

9. 3. Hardware/Software codesign for Digital Communication Processing • Target architecture model – Each layer of the system is based on two process: the transmit process : assembling the different field of the message in a given order. the receiver process: disassembling the different field of the incoming message in order to send either to the higher layer or some internal processing tasks.

10. 3. Hardware/Software codesign for Digital Communication Processing Generic architecture model of a layer

11. 3. Hardware/Software codesign for Digital Communication Processing 1.3 Graph Representation To express the message syntax and semantic of any communication protocol by graphs that specify the different transmit and receive process. In such graph node: representing a bit, a field, a frame or a packet with its associated processing tasks edge: indicating the next node => each node has associated data structure.

12. 3. Hardware/Software codesign for Digital Communication Processing 2. Hardware/Software Implementation 2.1 time based partitioning technique => to map the intermediate graph representation into different levels of the system. => each level is implemented following the target architecture model. => this implementation can be a reprogrammable based architecture or a hardwired one. => Depending on the interface communication time constraints between the different layer, specialized interface can be used to improve the channel throughput.

13. 3. Hardware/Software codesign for Digital Communication Processing 2.2 Hardware Synthesis this is performed by a scheduling and allocation method. – scheduling: to execute the operation in as few FSM states as possible. – allocation: to use as few hardware components as possible. 2.3 Software Synthesis the software component is implemented as a program running on the existing reprogrammable component.

14. 4. A Codesign Experiment in Acoustic Echo Cancellation 1. This Hardware/Software codesign approaches consist generally in HW/SW partitioning and scheduling, constrained code generation, hardware and interface synthesis. – HW/SW partitioning the main goal of the HW/SW partitioning is to find an assignment in hardware or software for all parts of the system specification.

15. 4. A Codesign Experiment in Acoustic Echo Cancellation – the objectives of scheduling: minimization of operators minimization of HW/SW communication minimization of execution time. – the aims of resource allocation: finding the type and number of resources used to implement the system. trying to share resources between functionalities. here, resources can be operator such as adder, FFT, register, FIFO, RAM.

16. 4. A Codesign Experiment in Acoustic Echo Cancellation 2. Allocation of arrays and code section the mapping of code and data section is great important to optimize resource utilization. the aim of internal/external allocation of code section and array: to assign to internal memories objects that have high utilization rates. it would be desirable to consider this operation during the partitioning step.

17. 4. A Codesign Experiment in Acoustic Echo Cancellation 3. Synthesis of communications synthesis of communications consists in determining for each HW/SW transfer. – the type of transfer (synchronous of asynchronous) – the needed hardware support and the associated protocol – the transfer mode ( DMA or memory mapped I/O)

18. 4. A Codesign Experiment in Acoustic Echo Cancellation – the minimization of the hardware area: using as much as possible synchronous transfer. – the choice of the transfer mode : DMA transfer mode and memory mapped I/O mode. => to ensure the best communication timing performance.

19. 4. A Codesign Experiment in Acoustic Echo Cancellation 4. Description of GMDFα GMDFα has good convergence and tracking performance and is a good candidate for echo cancellation. but for a long impulse response this algorithm involves numerous computations on a large set of data. => the real time implementation of the GMDFα algorithm constitutes a significant challenge for codesign methodology.

20. 4. A Codesign Experiment in Acoustic Echo Cancellation 4.1 Specification of GMDFα different parameters define the complexity of the GMDFα algorithm N: the block size K: the number of block L: the filter length R: new sample to be processed at each iteration of the algorithm α: overlapping factor

21. 4. A Codesign Experiment in Acoustic Echo Cancellation other parameters: data size, data type, data representation This oversampling implies an increased arithmetic complexity but allows a fast convergence rate.

22. 4. A Codesign Experiment in Acoustic Echo Cancellation Functional description

23. 4. A Codesign Experiment in Acoustic Echo Cancellation 4.2 Directed Acyclic Graph of the GMDFα In this DAG G=(N,A) node N: representing computation tasks. arcs A: describing data transfer and control precedence between two nodes. between two nodes, the precedence constraints are expressed by an arc. on each arc, the name and the volume of data are given. A dotted line means that this data will be used at the next iteration of the algorithm.

24. 4. A Codesign Experiment in Acoustic Echo Cancellation DAG of GMDFα

25. 4. A Codesign Experiment in Acoustic Echo Cancellation 4.3 Software implementation TMS320c30: real time implementation is difficult because of a medium length filter. this real time implementation is very slow, compared with the maximum run time. Two TMS320C40 interconnected by a parallel bus: the second process is active for only 50% of the total processing time, with a simplified version of GMDFα.

26. 4. A Codesign Experiment in Acoustic Echo Cancellation 4.4 Hardware implementation Using digital delay lines with an optimized area as memorization Element. => a read-write cycle in one clock cycle to be executed Enabling the operating unit to be used at maximum rate FFT, specific operation unit composed 2 multiplier with multiplexed input and one accumulator =>allowing the execution of ancomplex multiplication in only two clock cycles

27. 4. A Codesign Experiment in Acoustic Echo Cancellation 5. Codesign of GMDF α 5.1 Decomposition of GMDF α Summarization the execution times for various implementations

28. 4. A Codesign Experiment in Acoustic Echo Cancellation 5.2 HW/SW Partitioning of GMDFα The first implementation is a trade-off between execution time And hardware area.

29. 4. A Codesign Experiment in Acoustic Echo Cancellation The second partitioning minimizes the hardware operator area

30. 4. A Codesign Experiment in Acoustic Echo Cancellation 5.3 Allocation of arrays and code sections to DSP memory Number of clock cycle for N I/O operations and C CPU operation

31. 4. A Codesign Experiment in Acoustic Echo Cancellation HW/SW architecture for GMDFα

32. 4. A Codesig Experiment in Acoustic Echo Cancellation 6. Design result Delay due to communications are omitted. Data and code sections are mapped into external memories of the DSP. => Total execution times 12.5ms and 13.96ms => if location of array and code sections is optimized between external and internal memories the execution time of the second partitioning is reduced. => This point illustrates the importance of considering different software implementation of nodes.

33. 4. A Codesign Experiment in Acoustic Echo Cancellation Scheduling and elapse times of communications with DSP56002

34. 5. Hardware/Software Codesign for Communication System 1. This codesign methodology use gradual repartitioning approach, starting with an all software implementation or with a minimum predetermined hardware implementation. => seeking to accelerate software by extracting portion for implementation in hardware. => identifying the essential parameters needs for the hardware and software structure. => extracting the essential parameters (ex) execution time..

35. 5. Hardware/Software Codesign for Communication System => Designers predetermine which portions of the system are going to be implemented in hardware or using available component. ex) predetermined hardware component general purpose CPU, DSP chips, ASICs. => the cut and try procedure using gradual partitioning approach to apply to the remaining portion of the system.

36. 5. Hardware/Software Codesign for Communication System Proposed approach to system implementation

37. 5. Hardware/Software Codesign for Communication System 2. Partitioning and Performance Evalualtion – partitioning of theprocess model graph: during this step, certain processes are identified and extracted form the initial set of software processes to become hardware process. – estimating how many FPGAs or ASICs are needed: during this step, all designed harware processes are put together.

38. 5. Hardware/Software Codesign for Communication System 3. A DECT Example – RF part: predetermined to be implemented in hardware. – A/D and D/A conversion, ADPCM encoding and decoding: determined to use available component. – Baseband DSP part: VHDL behavior models – software part: services and management procedures

39. 5. Hardware/Software Codesign for Communication System HW/SW partitioning progress in a DECT example

40. 6. A Codesign Approach for communication systems 1. Starting the design process with a system-level specification. • Transforming a system-level specification – hardware/software partitioning communication synthesis architecture generation – The output of architecture generation: heterogeneous architecture represented by VHDL for hardware elements and represented by C for the software .

41. 6. A Codesign Approach for communication systems • description is finally mapped on a multiprocessor architecture. • mapping is achieved using standard code generator to transform C into assembler code for software part and synthesis tools in order to translate the VHDL into ASICs.

42. 6. A Codesign Approach for communication systems 2. System-level modeling for synthesis – Basic model communicating design unit(DU) communication operators known as channel units(CU) a set of transition tables modeled by the statetable operator(ST)

43. 6. A Codesign Approach for communication systems – Design unit design unit can contain a set of other design unit, channel unit, a set of transition tables. – Channel unit communication between sub-system(or Design Units) is performed using Channel Unit. – StateTable this operator is used to model process-level hierachy.

44. 6. A Codesign Approach for communication systems Basic model

45. 6. A Codesign Approach for communication systems 3. Hardware/Software architecture model this architecture serves as a platform onto which a mixed hardware/software system is mapped. this architecture is composed of three kinds of component. software components hardware components communication components

46. 6. A Codesign Approach for communication systems Flexible Architecture Platform

47. 6. A Codesign Approach for communication systems Example of an architecture

48. 6. A Codesign Approach for communication systems 4. An Example a Real-time Acquisition and Storage system(RTAS) the RTAS system performs the following tasks: receipt of an analog signal from 8 bit multiplexed wires. conversion of each analog signal into a digital signal. storage of the result into disk. the RTAS system is composed of two sub_systems communicating via a communication channel.

49. 6. A Codesign Approach for communication systems Real-time Acquisition and Storage System

50. 6. A Codesign Approach for communication systems 4.1 System modeling • RTAS system is composed of two communicating sub-system => Acquisition and Storage => Design unit • Net to connect two Design unit is Channel Unit this description is indepentant of the communication protocol.