1 / 16

STAR Pixel Detector readout prototyping status

STAR Pixel Detector readout prototyping status. Talk Outline. Quick review of requirements and system design Status at last meeting at IPHC RDO hardware status RDO firmware and software status Future development path. 2. RDO Requirements and Design.

kerry
Download Presentation

STAR Pixel Detector readout prototyping status

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. STAR Pixel Detectorreadout prototyping status

  2. Talk Outline • Quick review of requirements and system design • Status at last meeting at IPHC • RDO hardware status • RDO firmware and software status • Future development path LBNL-IPHC-06/2009 - LG 2

  3. RDO Requirements and Design In addition to the detailed requirements imposed by the interface to the sensors, the RDO system shall: Triggered detector system fitting into existing STAR infrastructure (Trigger, DAQ, etc.) Deliver full frame events to STAR DAQ for event building at approximately the same rate as the TPC (1 kHz for DAQ1000). Have live time characteristics such that the Pixel detector is live whenever the TPC is live. Reduce the total data rate of the detector to a manageable level (< TPC rate of ~1MB / event). Reliable, robust, cost effective, etc. Furthermore, this RDO system will be the basis of the future sensor testing including production probe testing so additional functionality will be included to enable this system to have the needed additional capabilities. LBNL-IPHC-06/2009 - LG 3

  4. Pixel Detector Design Cabling and cooling infrastructure New beryllium beam pipe (800 µm thick, r = 2 cm)‏ Mechanical support with kinematic mounts 2 layers 10 modules 4 ladders/module Detector extraction at one end of the cone Ladder with 10 MAPS sensors (~ 2×2 cm each) LBNL-IPHC-06/2009 - LG 4

  5. Functional Data Path – One Ladder buffer buffer This is a highly parallel readout system. 4 ladders per module (RDO motherboard). 10 modules in the PIXEL detector. 10 sensors 1 Ladder JTAG, CLK, CTL, markers LU protected power Digital hit data After power-on and configuration, the sensors are run continuously. Triggering is handled in the next stage of the RDO. LBNL-IPHC-06/2009 - LG 5

  6. Functional Data Path – Phase 1 Highly Parallel FPGA based RDO system • 40 sensor outputs/ladder • 4 ladders/module • 1 RDO board/module • 3 RDO boards for Phase-1 prototype test system Each received trigger enables an event buffer for one frame. The system is dead-time free up to the hardware limit of the number of buffers. LBNL-IPHC-06/2009 - LG 6

  7. Functional Data Path – Final (Ultimate) Highly Parallel FPGA based RDO system • 20 sensor outputs/ladder • 4 ladders/module • 1 RDO board/module • 10 RDO boards for system Same hardware with reconfigured firmware Each received trigger enables an event buffer for one frame. Triggered event boundaries are determined by data order. LBNL-IPHC-06/2009 - LG 7

  8. RDO System Design – Physical Layout Sensors, Ladders, Modules (interaction point) RDO Boards 1-2 m Low mass twisted pair Platform LU Protected Regulators, Mass cable termination 30 m Power Supplies 6 m - twisted pair 30 m DAQ Room Platform 100 m - Fiber optic DAQ PCs Control PCs (Low Rad Area) 30 m LBNL-IPHC-06/2009 - LG 8

  9. RDO Status as of 04/2008 LBNL-IPHC meeting LBNL-IPHC-06/2009 - LG 9 9

  10. RDO Status - Hardware Hardware – RDO motherboard – Fabricated, tested for individual sensor readout (analog and digital). 3 RDO systems loaded and tested. Mass termination board – Fabricated – under test. Full testing will commence with the readout of a 10 sensor ladder. 1 board loaded. LU protected power boards – Fabricated and tested. 5 boards loaded and tested. Low mass cable – Separate presentation. LBNL-IPHC-06/2009 - LG 10

  11. RDO Status – Firmware and Software                  Mimostar-3 Testing  Phase-1 Testing    Phase-1 ladder Testing  Same for all • Status as shown above. • Software is on a parallel path   See http://rnc.lbl.gov/hft/hardware/docs/Phase1/index.html for full documentation LBNL-IPHC-06/2009 - LG 11

  12. RDO Status – Firmware and Software • Phase-1 readout firmware and software are complete and working for analog and digital data for individual sensor testing. • DDL optical link and USB based data paths are both functional. • Analysis software for Phase-1 data is mostly complete. We are using both Root and Labview based analysis paths. • Scripting needed for automated testing of sensors is complete and working. • The analysis path for 10 sensor ladders is expected to be a simple extension of the existing framework. LBNL-IPHC-06/2009 - LG 12

  13. Adaptation of the existing individual testing system for use in automated probe testing. Development of the 10 sensor ladder readout firmware and software. Design and implementation of a slow control system for the detector. Extension of the system into multi-ladder / multi-sector readout. RDO Status – Future Development LBNL-IPHC-06/2009 - LG 13 13

  14. end LBNL-IPHC-06/2009 - LG 14 14

  15. Parameters and Data Rates Phase-1 Final (Ultimate) Raw data rate from sensors = 32 GB/sec Data rate to storage = 237 MB/sec (Scaled to full size detector) Data rate to storage = 199 MB/sec Note: Data rates for hit data only for Au-Au central collisions including peripheral collision electrons. Sensor noise is not included. LBNL-IPHC-06/2009 - LG 15

  16. This is the block diagram of firmware structure of pixel readout board Thick arrow means connection to outside of FPGA Block which connects to outside of FPGA includes IO pins and controller. Cross lines denotes NO connection. Temperature ADC ADC LVDS SPARE IO SRAM controller Internal processor(contact outside by SPARE IO) Frame FIFO Event builder Global control register(access every module) TCD Command decoder DDL Controller USB Controller LBNL-IPHC-06/2009 - LG 16 16

More Related