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Logic Simulator for Combinational Circuit

Logic Simulator for Combinational Circuit. Jie Qin Dept. of Electrical and Computer Engineering Auburn University, AL 36849, USA. Problem Statement. Develop a logic simulator with support for the standard bench format and the hierarchical bench format.

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Logic Simulator for Combinational Circuit

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  1. Logic Simulator for Combinational Circuit Jie Qin Dept. of Electrical and Computer Engineering Auburn University, AL 36849, USA ELEC 7250 Final Project: Jie Qin

  2. Problem Statement • Develop a logic simulator with support for the standard bench format and the hierarchical bench format. • When the output of the simulated circuit does not match the expected response, try to diagnose the error in the circuit using the logic simulator. ELEC 7250: Jie Qin

  3. Logic Simulator • The implemented logic simulator consists of a compiler and a simulator. -- the compiler reads in a circuit description in bench format and builds a simulation table in memory. -- the simulator propagates the values provided from outside at the PIs to the POs utilizing the simulation table (logic propagation). ELEC 7250: Jie Qin

  4. A simulation table is actually a list of gate records. All the PIs, gates and POs in a circuit are represented by the gate records in the implemented logic simulator. A gate record includes the following information. Simulation Table ELEC 7250: Jie Qin

  5. An Example of Simulation Table before logic propagation gate “d” gate “e” PI “a” PO “f” f a d e ELEC 7250: Jie Qin

  6. Logic Propagation • To propagate the known value at the PIs to the POs, two lists are maintained in the memory. -- passive list: it includes all the “gate records” whose outputs are in unknown states. -- active list: once a gate has its output in known state, it will be append to this list. However, after all the fanouts of this gate are determined as a known value, it will be removed from this list. ELEC 7250: Jie Qin

  7. An Example of Logic Propagation 0 g 0 0 0 0 1 a 1 c e 1 1 1 0 1 1 f h 1 1 d b Half-Adder active list passive list c d a e f b g h ELEC 7250: Jie Qin

  8. Results for a 4-bit Ripple Adder ELEC 7250: Jie Qin

  9. Results for ISCAS’85 Circuits ELEC 7250: Jie Qin

  10. Fault Diagnosis • Assumption #1: the internal state of the CUT cannot observed from the outside • Assumption #2: the possibility of single fault is much higher than multiple faults • Approach: -- Step #1: for each faulty PO, obtain a reversed logic cone from PO; -- Step #2: intersect the logic cones obtained in Step #1; -- Step #3: try more test vectors to obtain a logic cone as small as possible. ELEC 7250: Jie Qin

  11. Conclusion • The execution time increases with the number of gates and the number of test vectors. • The fault diagnosis still needs to be improved because the assumption does not match the real situation very well. ELEC 7250: Jie Qin

  12. Thankyou! ELEC 7250: Jie Qin

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