Dynamic Logic Circuits

1. Static logic circuits allow implementation of logic functions based on steady state behavior of simple nMOS or CMOS structures. All valid output levels in static gates are associated with steady state operating points of the circuit in question. This detects that a certain time delay be allowed before the output corresponding to the applied input(s) can be valid. The output level is preserved as long as the power supply is provided. In high density, high-performance digital implementations where reduction of circuit delay and silicon area are objectives dynamic circuits offer several advantages over static logic circuits. Operation of dynamic logic gates depends on temporary (transient) storage charge in parasitic node capacitances instead of steady state behavior. This operational property necessitates updating of internal node voltage levels since charge in a capacitor cannot be retained indefinitely. Dynamic circuits require periodic clock signals for control of charge refreshing. Dynamic Logic Circuits

2. Temporarily storing a state at capacitive nodes permits for implementation of simple sequential circuits with memory functions. Use of common clocks throughout the system allows for synchronization of operations in various circuit blocks. The D-latch static D-Latch studied earlier in the semester can now be implemented using dynamic circuits as shown below. The hold operation is occurs when the clock is low and charge is temporarily stored in the parasitic capacitance Cx. Correct operation depends on how long charge can be retained at node X, before the output state changes due to charge leakage. Dynamic Logic Circuits

3. In many structures a bus can be modeled as a capacitor Cb. The voltage on this bus might be sampled from time to time (e.g. writing the data on the bus into memory). In general we can represent the capacitances associated with this bus as Cb and Cs . The charge associated with each capacitor before closing the switch is described by Qb = CbVb and Qs = CsVs. The total charge QT is described by QT = CbVb + CsVs The total capacitance CT is given by: CT = Cb + Cs . When the switch is closed the resultant voltage VR is: Charge Sharing bus Vs Vb Cb Cs

4. If Vb = VDD and Vb >>Vs then the desired voltage VR is: To ensure proper data transfer from Cb to Cs, we must have that Cs << Cb . The charge sharing problem is prominent in dynamic circuits Charge Sharing