Latch/Register Scheduling Under Process Variation

1. Latch/Register Scheduling Under Process Variation Aaron Hurst EE 290a, Spring 2005

2. D1 4 6 ok ? 4 D2 ok fail 6  2 D2 D1 Review • Latch timing is more tolerant to post-manufacturing process variation R1 ? R3 D1 D2 d=1 T=5 D1= D2 = {4,6},P(each) = 50%

3. Review • No edge-triggered schedule can match level-sensitive yield • Optimal schedule varies from manufactured device to device • We don’t know at design-time where to schedule latch points • Can not be quantified with static timing analysis • Effect is lost in worst-case analysis • Either it will or will not fail

4. Goal • Measure the yield of a scheduled design (verification problem) • Find the latch schedule that maximizes yield (optimization problem) General Problem • For each latch, find  and  to maximize yield Single duty clock Problem • Find a global w, and a  for each latch (where  = + w)to maximize yield L    

5. Verification • Two methods for verifying a latch schedule • Iterative [SMO 90] • Start by assuming the earliest departure times • Find the actual arrivals at latch inputs • Iterate until a fixpoint is reached • Structural [Szymanski 92] • Construct a constraint graph • Search for negative cycles in the graph • Can be extended into statistical domain [Zhou 04]

6. Verification – Iterative Method • Iteration based upon well-researched foundation • Statistical timing analysis vs. negative cycle detection • Central questions: • Does iteration converge for a statistical arrival times? • Does iteration converge for an approximation of statistical arrival times?

7. Verification - Iterative • max(A,  ) • Inaccuracy less of a problem in general timing analysis, when both operands of the max() function have similar s

8. Verification – Results • Result: algorithm does converge! • As expected, rate of convergence highly dependent on the target period • Need: more formal proof…

9. Optimization - A Special Case • If w=0 (i.e. the latches are edge-triggered), the departure time is independent of the arrival time • Both the verification and optimization problems become much easier • Can solve a standard optimization problem L Dl Al find t, maximize where T is the clock period t is a clock schedule d is the min path delay D is the max path delay

10. Optimization - Results • Conjunction of inequalities can be approximated using the max function of [Clark 61] • Use conjugate gradient to maximize

11. Optimization - General • If w≠0, there are cyclic timing dependencies • Idea 1: Cut circuits at points where arrival time is least likely to arrive in transparent window • Idea 2: Optimize “sections” of paths using a method similar to [Zhou 04]

12. Conclusions • General techniques in statistical timing analysis need work • Verification problem is hard • Optimization problem is harder