Introduction to PLD.

1. PLD Introduction to PLD. Presented by:

2. Contents: • Idea; • History; • High-Capacity PLD’s Architecture & Overview of ALTERA PLD; • Computer aided design (CAD) flow for PLD • Introduction to VHDL/VerilogHDL; • Getting started.

3. Contents: • Idea; • History; • High-Capacity FPGA’s Architecture & Overview of ALTERA FPGA; • Computer aided design (CAD) flow for PLD • Introduction to VHDL/VerilogHDL; • Getting started.

4. Idea – Definition. Today a chips are distributed into three groups: ASIC’s (Application Specific Integrated Circuits) Chips with hardware realization of data processing algorithms (microprocessors & microcontrollers) FPGA & CPLD

5. Idea – Definition. A programmable logic device can be defined as … an integrated circuit containing configurable logic and/or storage elements, which are linked together using programmable interconnect In general the following resources are distinguished: • Logic; • Interconnect; • I/O.

6. Idea – Details. • One or more resources are configurable; • Reprogrammable or in system programmable (ISP); • Reduces design and debug cycle • Allows field upgrades of existing logic systems • A small amount of fault tolerance • Raises thepossibility of reconfigurable computing – but there are still many problems to be solved before this is realized • Nowadays configuration of all resources; • Special structures added to the devices, like RAMs, DLLs, …

7. Idea - Advantages of PLDs. The programmability offers: • Short development time; • Short turnaround time; • Rapid prototyping; • Flexibility with respect to engineering change orders; • Save board space; • Small NRE (non recurring engineering ) costs.

8. Contents: • Idea; • History; • High-Capacity FPGA’s Architecture & Overview of ALTERA FPGA; • Computer aided design (CAD) flow for PLD • Introduction to VHDL/VerilogHDL; • Getting started.

9. A B C Programmable switch or fuse OR plane AND plane History – PLA. The first device developed specifically for implementing logic circuits was PLA. A PLA consists of two logic gates levels: • programmable “wired” OR-plane; • programmable “wired” AND-plane.

10. A B C AND plane History – PAL. Programmable switch or fuse PALs feature only a single level of programmability, consisting of a programmable “wired” AND-plane that feeds fixed OR-gates.

11. B A C Select Enable Flip-flop MUX D Q Clock AND plane History – SPLD. All small PLDs, including PLAs, PALs, and PAL-like devices are grouped into a single category called Simple PLDs (SPLDs), whose most important characteristics are low cost and very high pin-to-pin speed-performance.

12. I/O Block PLD Block PLD Block I/O Block Interconnection Matrix Interconnection Matrix I/O Block PLD Block PLD Block I/O Block History – CPLD. The way to provide large capacity devices is to integrate multiple SPLDs onto a single chip and provide interconnect to programmable SPLD blocks together. PLD that has this basic structure are referred as Complex PLDs (CPLDs).

13. Logic block Interconnection switches I/O I/O I/O I/O History - FPGA. FPGAs comprise an array of uncommitted circuit elements, called logic blocks, and interconnect resources. FPGA configuration is performed through programming by the end user. FPGAs are only one type of PLD that supports very high logic capacity, It has been responsible for a major shift in the way digital circuits are designed!

14. CPLDs often consist of a limited set of complex reconfigurable blocks - Complex Programmable Logic Device consists of multiple SPLD blocks that are interconnected to realize larger digital systems FPGAs are configured at a fine grain level from many equivalent logic blocks or array of configurable gates - Field Programmable Gate Array has narrower logic choices and more memory elements. LUT (Lookup Table) may replace actual logic gates. High-Capacity PLDs Architecture. Difference between FPGAs and CPLDs PLD CPLD FPGA

15. I/O Block PLD Block PLD Block I/O Block I/O I/O I/O Interconnection Matrix Interconnection Matrix I/O Block PLD Block PLD Block I/O Block I/O High-Capacity PLDs Architecture.Difference between FPGAs and CPLDs CPLD FPGA

16. History - important terminology.Definitions of Relevant Terminology: • CPLD — a Complex PLDthat consists of an arrangement of multiple SPLD-like blocks on a single chip; • FPGA — a Field-Programmable Gate Arrayis an PLD featuring a general structure that allows very high logic capacity; • Interconnect— the wiring resources in an PLD; • Programmable Switch— a user-programmable switch that can connect a logic element to an interconnect wire, or one interconnect wire to another; • Logic Cell– The basic building block of an Altera device • Macrocell – The basic building block of Product Term-based device MAX9000, MAX7000

17. History - important terminology. • Logic Element – The basic building block of Look-Up Table-based device FLEX10K, FLEX8000, FLEX6000 • Logic Array Block (LAB) – A collection or group of logic cells • Logic Capacity— the capacity of an PLD is measured by the size of gate array which is comparable to logic capacity. It can be thought as “number of 2-input NAND gates”; • Logic Density— the amount of logic blocks per unit area in an PLD. • Speed-Performance— measures the maximum operable speed of a circuit when implemented in an PLD.

18. History - Overview. 1967 - Fairchild’s “Micromosaic” Early 70’s - First appearance of PLDs Late 70’s - Arrival of CPLDs 1985 - First SRAM based devices Late 80’s - Arrival of FPGAs 1991 - ISP (Lattice) 1998 - First 1 million gates device 2000 - First 3 million gates device 2005 - First 10 million gates device The chart summarizes the categories of FPDs by listing the logic capacities available in each of the three categories.

19. Contents: • Idea; • History; • High-Capacity FPGA’s Architecture & Overview of ALTERA FPGA; • Computer aided design (CAD) flow for PLD • Introduction to VHDL/VerilogHDL; • Getting started.

20. FPGA building blocks: Programmable logic blocksImplement combinatorial and sequential logic. Based on programmable logic (LUT) and DFF. Look Up Tables made from small RAM cells. Programmable logic blocks can also be used as small memory blocks Programmable interconnectWires to connect inputs and outputs to logic blocks. Programmable interconnects using switching matrixes. Several types of interconnects: clocks, short distance local connections, long distance connections across chip Programmable I/O blocksSpecial logic blocks at the periphery of device for external connections. I/O buffers have various voltage support and tri-state option. Logic block Interconnection switches I/O I/O I/O I/O FPGA - Generic Structure

21. High-Capacity PLDs Architecture. Today’s FPGA Devices Meet Embedded System Requirements • Embedded RAM • Wide range of fast I/O • High-performance Digital Signal Processing (DSP) blocks • Abundant logic • Substantial embedded memory • Low Cost FPGA and Structured ASIC families • Soft Processor cores

22. ALTERA Cyclone II FPGA Overview • Highest Density • 68K Logic Elements(700K ASIC Gates) • Highest Performance • High-Performance DSP • 250 MHz Performance • Embedded Systems • Software Nios II Processor

23. ALTERA Cyclone II FPGA Architecture Features: • 90-nm dielectric process • High density architecture with 4,608 to 68,416 LEs • Up to 1.1 Mbits of RAM • True dual-port operations (one read one write, two reads or two writes) for x1, x2, x4, x8, x16 and x18 modes • Variable port configurations (x1, x2, x4, x8, x16, x32 and x36) • Up to 260MHz operation • Embedded Multipliers • Advanced I/O support • Flexible clock management circuitry • Hierarchical clock network for up to 402.5 MHz • Up to 4 PLLs • Up to 16 global clock lines

24. Overview ofALTERA Cyclone II Device EmbeddedMultipliers Logic Array Side I/OElements with Support for PCI/PCI-X& MemoryInterfaces M4K MemoryBlocks Top & BottomI/O Elements with Support forMemory Interfaces Phase-LockedLoops

25. MUX LUT 1 D0 Flip-flop 1 D1 Y D Q 0 D2 S0 Clock S1 D3 1 CLR High-Capacity FPDs Architecture.Configurable logic • Logic resources arranged in arrays or in rows. • Logic blocks hold large or small amount of logic (fine grained architecture)

26. LUT A B Z A C D B Z C D Look-Up Tables (LUT) • LUT with N-inputs can be used to implement any combinatorial function of N inputs • LUT is programmed with the truth-table LUT implementation Truth-table Gate implementation

27. X1 X2 0/1 0/1 0/1 0/1 F 0/1 0/1 0/1 0/1 X3 LUT Implementation • Example: 3-input LUT • Based on multiplexers (pass transistors) • LUT entries stored in configuration memory cells Configuration memory cells

28. Look-up table (LUT) to implement combinatorial logic Register for sequential circuits Additional logic (below): Carry logic for arithmetic functions Expansion logic for functions requiring more than 4 inputs REG ALTERA Cyclone IILogic Element LUTChain CarryIn0 CarryIn1 RegisterChain LocalRouting In1In2In3In4 LUT General Routing General Routing Clock Carry Out0 Carry Out1 RegisterChain The basic logic block, called a Logic Element (LE) contains a four input LUT, a flip-flop, and special-purpose carry circuitry for arithmetic circuits. The LE also includes cascade circuitry that allows efficient implementation of wide AND functions.

29. D DATA Logic Element: Normal Mode LUT Chain Input Register Chain Input Register Control Signals addnsub cin (2) data1 4-Input LUT Sync Load & Clear Logic data2 Row, Column & DirectLink Routing data3 data4 Local Routing Register Feedback LUT Chain Output Register Chain Output The normal mode is suitable for general logic applications and wide decoding functions that can take advantage of a cascade chain. In normal mode, four data inputs from the LAB local interconnect and the carry-in signal are the inputs to a 4-input LUT.

30. D DATA Logic Element: Dynamic Arithmetic Mode Register Chain Input Register Control Signals LAB Carry-In Carry-In Logic Carry-In0 Carry-In1 addnsub data1 Sum Calculator Sync Load & Clear Logic data2 Row, Column & DirectLink Routing data3 Carry Calculator Local Routing Carry-Out Logic Carry-In0 Carry-In1 Register Chain Output The arithmetic mode offers two 3-input LUTs that are ideal for implementing adders, accumulators, and comparators. One LUT provides a 3-bit function; the other generates a carry bit. Carry-Out1 Carry-Out0

31. A B S Ci Co Dynamic Arithmetic ModeFull adder S = (A xor B) xor C Co = (A * B) + (C*(A xor B))

32. A B S D DATA Ci Co Logic Element: Dynamic Arithmetic Mode Register Chain Input Register Control Signals LAB Carry-In Carry-In Logic Carry-In0 Carry-In1 addnsub data1 Sum Calculator Sync Load & Clear Logic data2 Row, Column & DirectLink Routing data3 Carry Calculator Local Routing Carry-Out Logic Carry-In0 Carry-In1 Register Chain Output Carry-Out1 Carry-Out0

33. D0 D2 D1 Flip-flop Flip-flop A B Flip-flop D Q D Q D Q R R Reset clk R D2 D1 D0 COUT CIN Flip-flop Flip-flop Flip-flop D Q D Q D Q R R R Reset clk Counters Ripple counter Ripple carry counter is not recommended in FPGA designs due to their asynchronous nature D0 = Q0 xor Cin C0 = Q0 and Cin Ripple-carry counter Synchronous design

34. D2 D1 D0 COUT CIN Flip-flop Flip-flop Flip-flop D Q D Q D Q R R R Reset clk D DATA Dynamic Arithmetic ModeRipple-carry counter Register Chain Input Register Control Signals LAB Carry-In Carry-In Logic Carry-In0 Carry-In1 addnsub data1 Sum Calculator Sync Load & Clear Logic data2 Row, Column & DirectLink Routing data3 Carry Calculator Local Routing Carry-Out Logic Carry-In0 Carry-In1 Register Chain Output Carry-Out1 Carry-Out0

35. Dynamic Arithmetic ModeComparator A=B if A(0) = B(0) and A(1) = B(1) … and A(n-1)=B(n-1) or AeqB = (A(0) xnor B(0)) and (A(1) xnor B(1)) and ….etc. B(2) B(1) B(0) A(2) A(1) A(0) B(2) B(1) A(2) A(1) B(0) A(0) A eq B A eq B

36. Logic Array Blocks (LAB) • Control Signals: • 2 CLK • 2 CLK EN • 2 ACLR • 1 SCLR • 1 SLOAD Direct link interconnect from left and right LAB, MK4 memory block, embedded multiplier, PLL or IOE output 4 • 16 LEs • Local Interconnect • LAB Control Signals • LE carry chains • Register chains LE1 4 LE2 4 LE3 Direct link interconnect to left (up to 48 LEs) Direct link interconnect to right (up to 48 LEs) 4 LE4 Fast Local Interconnect 4 LE13 4 LE14 4 30 LAB Input Lines 10 LE Feedback Lines LE15 4 LE16

37. High-Capacity PLDs Architecture.Several types of configurable interconnects Before Programming After Programming Switch matrix • 6 pass transistors per switch matrix interconnect point • Pass transistors act as programmable switches • Pass transistor gates are driven by configuration memory cells Interconnect point

38. Programmable Interconnect Interconnect hierarchy (not shown) • Fast local interconnect • Horizontal and vertical lines of various lengths LE LE LE Switch Matrix Switch Matrix LE LE LE

39. High-Capacity PLDs Architecture.Several types of I/O • In/out/tri-state; • Flip-flops, latches; • Pull-up/pull-down; • DDR; • Series resistors; • Bus keeper; • Drive strength control; • Slew rate control; • Single ended/differential. Configurability of the user I/O varies to a great extent there are dedicated pins for power and configuration some of the user I/O pins may be reserved for special function during configuration.

40. High-Capacity FPDs Architecture.Several types of I/O Enable Flip-flop From array D Q Clock Flip-flop • Several low-voltage I/O standards; • Mixed voltage I/O bank capability; • Delay lines; • Boundary scan (JTAG); • Differential I/O. To array Q D Clock

41. Basic I/O Block Structure Three-State Q D Three-StateControl Clock Output Q D Output Path Direct Input Input Path Registered Input Q D

42. I/O Bank I/O Bank Numbers & Locations

43. High-Capacity FPDs Architecture.Special structures • On chip RAMs and ROMs: • Nearly all vendors offer devices with on chip RAM Blocks; • RAM blocks may be cascaded; • RAM blocks can be configured in different ways (single ported, dual ported, synchronous, asynchronous, CAM). • Clock management - on chip DLLs or PLLs: • High end devices have up to 8 DLLs/PLLs on chip; • Used to deskew on/off chip clock signals (e. g. to RAM banks); • Provide clock division and multiplication capabilities; • DLLs have a minimum operating frequency. • DSP options and applications: • On chip Multipliers; • On chip MACs. • On chip Microprocessor Cores; • Support for various interface standards • High-speed serial I/Os • Boundary Scan/JTAG.

44. CycloneII Embedded Memory Port A Port B • 4-Kbit Blocks • 250-MHz Performance • Fully Synchronous • True Dual-Port Mode • Simple Dual-Port Mode • Single-Port memory • Flexible Capabilities • Mixed-Clock Mode • Mixed-Width Mode • Shift Register Mode • Read-Only Mode • Byte Enables • Initialization Support DATAADDRWRENCLKCLKENA OUTCLR DATAADDRWRENCLKCLKENA OUTCLR

45. Block RAM Port Aspect Ratios 1 2 4 8 512 x 8 1k x 4 8+1 2k x 2 512k x (8+1) 16 256 x 16 16+2 4k x 1 256 x (16+2) 32 128 x 32 32+4 128 x (32+4)

46. Overview of ALTERA PLDs.Embedded Array Block Combine EABs to create larger blocks EAB size is flexible

47. Global Clock Network & Phase-Locked Loops • Clock management is important within digital systems design • High speed designs require low latency, low skew clock solutions • Low latency – a minimum propagation delay time throughout the device • Low skew – a minimum difference between actual clock edges as seen on various points on the device • Sources for clock skew? • Cyclone II devices provide the following for clock management • A global clock network • Up to four phase-locked loops (PLLs)

48. 4 2 GCLK CLK[15..12] CLK[3..0] CLK[11..8] 1 3 CLK[7..4] PLLs and global clock network • 16 Total Nets • Used as Clock Sources for All Device Blocks • Fed by • Dedicated Clock Pins • PLL Outputs • Internal Logic

49. Phase-Locked Loops (PLLs) • A PLL is a closed-loop feedback control system that maintains a generated signal in a fixed phase relationship to a reference signal • Applications include: • Frequency synthesizers for digitally-tuned radio receivers and transmitters • FM and AM radio signal demodulation • Clock multipliers in digital systems that allow internal elements to run faster (or slower) than external connections, while maintaining precise timing relationships (our basic application in this course) • Cyclone II PLLs provide general-purpose clocking with clock multiplication and phase shifting as well as outputs for differential I/O support

50. LockDetect I/O & Global Routing N Reference Clock PFD CPLF VCO G0 GlobalClockNetwork G1 M I/OBuffer EG Cyclone II PLL DetailsBasic PLL Operation • The main purpose of a PLL is to synchronize the phase and frequency of a voltage controlled oscillator (VCO) to an input reference clock • There are a number of components that comprise a PLL to achieve this phase alignment • The PLL compares the rising edge of the reference input clock to a feedback clock using a phase-frequency detector (PFD) • The PFD produces an up or down signal that determines whether the VCO needs to operate at a higher or lower frequency • The PFD output is applied to a charge pump and loop filter, which produces a control voltage for setting the frequency of the VCO • If the PFD transitions the up signal high, then the VCO frequency increases • If the PFD transitions the down signal high, then the VCO frequency decreases