A Reduced Complexity Algorithm for Minimizing N -Detect Tests

1. A Reduced Complexity Algorithm for Minimizing N-Detect Tests Kalyana R. Kantipudi Vishwani D. Agrawal Department of Electrical and Computer Engineering Auburn University, AL 36849 USA 20th Intl Conf. on VLSI Design, Bangalore, Jan 6-10th, 2006 VLSI Design 2007

2. Motivation for This Work • Ability of N-detect tests to improve the defect coverage. • Easy assimilation of N-detect tests into the normal test generation strategy. • Main limitation of N-detect tests is their size. • Inability of ILP based method to produce a time-bound optimal solution. • Inability of previous test minimization strategies in finding minimal tests for c6288 benchmark. VLSI Design 2007

3. Outline • ILP based N-detect test minimization • Previous LP based methods • Recursive rounding based approach • The 3V3F example • Minimal tests for c6288 • Results • Conclusions VLSI Design 2007

4. ILP-Based N-Detect Test Minimization [1] • Use any N-detect test generation approach to obtain a set of k vectors which detect every fault at least N times. • Use diagnostic fault simulation to get the vector subset Tj for each fault j. • Assign integer variable ti to ith vector such that, • ti = 1 if ith vector is included in the minimal set. • ti = 0 if ith vector is not included. [1] K. R. Kantipudi and V. D. Agrawal, “On the Size and Generation of Minimal N-Detection Tests,” Proc. VLSI Design’06. VLSI Design 2007

5. Objective and Constraints of ILP Where, Nj is the multiplicity of detection for the jth fault. Nj can be selected for each individual fault based on some criticality criteria or on the capability of the initial vector set. ILP always generates an optimal solution for the given set of test vectors. VLSI Design 2007

6. A Linear Programming Approach • Though ILP guarantees an optimal solution, it takes exponential time to generate the solution. • Time bounded ILP solutions deviate from optimality. • LP takes polynomial time (sometimes in linear time) to generate a solution. • Redefining the variables tis as real variables in the range [0.0,1.0] converts the ILP problem into a linear one. • The problem now remains to convert it into an ILP solution. • The optimal value of the relaxed-LP of the ILP minimization problem is a lower bound on the value of the optimal integer solution to the problem. VLSI Design 2007

7. Previous Solutions (Randomized rounding) • The real variables are treated as probabilities. • A random number xi uniformly distributed over the range [0.0,1.0] is generated for each variable ti. • If ti≥ xi then ti is rounded to 1, otherwise rounded to 0. • If the rounded variables satisfy the constraints, then the rounded solution is accepted. • Otherwise, rounding is again performed starting from the original LP solution. VLSI Design 2007

8. Limitations of Randomized Rounding • Consider three faults f1,f2 and f3, and three vectors. • We assign a real variable ti to vector i. • Now the single detection problem is specified as: • Minimize t1 + t2 + t3 • Subject to constraints, • f1 : t1 + t2≥ 1 • f2 : t2 + t3 ≥ 1 • f3 : t3 + t1 ≥ 1 • The number of tests is much larger than the size of the minimal test set. • The randomized rounding becomes a random search. VLSI Design 2007

9. Recursive Rounding (New Method) • Step 1: Obtain an LP solution. Stop if each ti is either 0.0 or 1.0 • Step 2: Round the largest ti and fix its value to 1.0 If several ti’s have the largest value, arbitrarily set only one to 1.0. Go to Step 1. • Maximum number of LP runs is bounded by the final minimized test set size. • Final set is guaranteed to cover all faults. • This method takes polynomial time even in the worst case. • LP provides a lower bound on solution. Lower Bound ≤ exact ILP solution ≤ recursive LP solution Absolute optimality is not guaranteed. VLSI Design 2007

10. The 3V3F Example • Step 1: LP gives t1 = t2 = t3 = 0.5 • Step 2: We arbitrarily set t1 = 1.0 • Step 1: Gives t2 = 1, t3 = 0 ■ or t2 = 0, t3 = 1 ■ or t2 = t3 = 0.5 • Step 2: (last case) We arbitrarily set t2 = 1.0 • Step 1: Gives t3 = 0 VLSI Design 2007

11. Minimal Tests for Array Multipliers • There exists a huge difference between its theoretical lower bound of six and its practically achieved test set of size 12. • A 15 x 16 matrix of full-adders (FA) and half-adders (HA). • To make use of its recursive structure and apply linear programming techniques. VLSI Design 2007

12. Tests for c6288: 16-Bit Multiplier • Known results (Hamzaoglu and Patel, IEEE-TCAD, 2000): • Theoretical lower bound = 6 vectors • Smallest known set = 12 vectors, 306 CPU s • Our results: • Up to four-bit multipliers need six vectors • Five-bit multiplier requires seven vectors • c6288 • 900 vectors constructed from optimized vector sets of smaller multipliers • ILP, 10 vectors in two days of CPU time • Recursive LP, lower bound = 7, optimized set = 12, in 301 CPU s VLSI Design 2007

13. Comparison of ILP and Recursive LP VLSI Design 2007

14. Sizes of 5-Detect Tests for ISCAS85 Circuits VLSI Design 2007

15. CPU Time to Minimize 5-Detect Tests VLSI Design 2007

16. Optimized 15-detect Tests [1] K R Kantipudi and V D Agrawal, Proc. VLSI Design, 2006 [2] Lee, Cobb, Dworak, Grimaila and Mercer, Proc. DATE, 2002 VLSI Design 2007

17. Conclusion • Single and N-detection tests can be efficiently minimized by the new procedure. • The quality of the result from recursive rounding LP is close to that of ILP. • The 10 vector test set for c6288 signifies the shortcomings of present test set minimization techniques. • The recursive rounding LP method has numerous other applications where ILP is traditionally used and is found to be expensive. VLSI Design 2007

18. Thank You . .. VLSI Design 2007