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Digital Electronics

Digital Electronics. Counters. COUNTER UNIT. Asynchronous up and down counters Asynchronous modulus counters Synchronous Counters. COUNTERS CHARACTERISTICS. 1. MODULUS- number of counts in one cycle. 2. Up or down count. 3. Asynchronous or synchronous operation.

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Digital Electronics

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  1. Digital Electronics Counters

  2. COUNTER UNIT Asynchronous up and down counters Asynchronous modulus counters Synchronous Counters

  3. COUNTERS CHARACTERISTICS 1. MODULUS- number of counts in one cycle 2. Up or down count 3. Asynchronous or synchronous operation 4. Free running or self stopping

  4. ASYNCHRONOUS COUNTERS • Only LSB flip-flop controlled by the clock input • Also known as a RIPPLE COUNTER • Two or more “T” flip-flops interconnected, output • of each flip-flop connected to clock input of the next. • Modulus- number of stable states in each flip-flop cycle • Modulus = N= number of flip-flops • Highest number in count =

  5. BUILD A 4 BIT RIPPLE COUNTER 1. 4 JK flip-flops in toggle mode- all JK inputs tied high 2. Q outputs connected to clock input of following flip-flop 3. FF A = LSB (one with clock input); toggles when input clock toggles from high to low; FF D = MSB 4. FF B, C, D do not toggle till receive NGT from proceeding FF 5. Direction of count can be reversed by complementing each FF’s output or complementing each FF’s input

  6. TEST 1. What is the term for the number of counts in one counter cycle? Modulus of the counter 2. How is the modulus determined? 3. Since only the first flip-flop of a ripple counter is controlled by a clock, the counter is ____________________? Asynchronous 4. What is the mod number of a counter containing 5 flip-flops? 32 5. What is the highest count of a four bit counter? 31

  7. 1. Determine smallest number of FF’s such that thus 4 FF’s are required 1 1 0 0 BUILD A COUNTER THAT COUNTS FROM ZERO TO NINE (X=MOD 10) 2. Connect a NAND gate to asynchronous clears of all FF’s 3. Determine which FF’s will be high at count = X Connect the Q outputs of these FF’s to NAND gate inputs

  8. ASYNCHRONOUS DOWN COUNTER • Direction of count can be reversed by • (a) complementing each FF’s output or • (b) complementing each FF’s input

  9. DIGITAL CLOCK

  10. COUNTERS ASYNCHRONOUS SYNCHRONOUS

  11. SYNCHRONOUS COUNTERS • Two or more FF’s connected as “T” FF’s. • All FF’s in the counter are clocked at the same time. • Advantage over the ripple counter is speed and accuracy but more complex.

  12. SYNCHRONOUS COUNTERS MOD <2 N • A NAND control gate is used to clear the counter before the full count.

  13. SYNCHRONOUS COUNTERS UP/DOWN

  14. RIPPLE COUNTER Binary Output Clock Input 1 0 0 0 0 1 1 1 0 1 1 0 0 0 1 0 0 0 0 0 0 0 1 1 0 1 0 1 0 0 0 1 0 1 0 0 Pulse 5 Pulse 8 Pulse 7 Pulse 6 Pulse 4 Pulse 1 Pulse 2 Pulse 3 This 4-bit counter has 16 states and will count from binary 0000 through 1111 and then reset back to 0000. The counter has amodulus of 16. On the next clock pulse (8) all FFs will toggle because each will receive aH-to-Lpulse- one after another. Watch the count ripple thru the counter. PS and CLR input are INACTIVE All J-K flip-flops in the TOGGLE MODE

  15. Clock input 1s output 2s output 4s output RIPPLE COUNTER WITH WAVEFORMS Binary Output Clock Input 0 0 1 1 0 1 0 0 0 0 0 1 0 1 0 1 0 0 1 0 0 0 0 0 Pulse 5 Pulse 1 Pulse 2 Pulse 3 Pulse 4 FFs triggered on H-to-L pulse. CLK toggles 1s FF. 1s FF toggles 2s FF. 2s FF toggles 4s FF.

  16. Short negative pulse To clear input of each FF DECADE COUNTER Initial count at 0111 Binary Output Clock Input 1 0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0 1 1 1 0 1 0 0 0 1 0 1 1 0 0 0 0 0 1 1 Pulse 7 Pulse 6 Pulse 5 Pulse 4 Pulse 3 Pulse 2 Pulse 1 Pulse 8 All J & K inputs = 1 All PR inputs = 1 Count is at 1001. Next clock pulse will increment counter for a short time to 1010 which will activate the NAND gate and reset the counter to 0000. To change mod-16 counter to decade counter: Reset count to 0000 after 1001 (9) count. When count hits 1010 reset to 0000. See added 2-input NAND gate that clears all JK FFs to 0 when count hits 1010.

  17. DOWN COUNTER Initial count set at binary 111 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 Pulse 4 Pulse 2 Pulse 1 Pulse 3 Pulse 5 Changes from Ripple Up Counter are wiring from Q’ outputs (instead of Q outputs) to the CLK input of the next FF.

  18. SELF-STOPPING DOWN COUNTER Watch count on Pulse 8. The count remained at binary 000. 1 1 0 1 0 0 1 0 1 1 1 1 0 0 1 0 0 0 0 1 0 0 1 1 Pulse 2 Pulse 4 Pulse 3 Pulse 1 Pulse 5 Pulse 6 Pulse 8 Pulse 7 This is a 3-bit down counter. The 1s FF is in TOGGLE mode when counting (J & K = 1). The 1s FF switches to HOLD mode when the J and K inputs are forced LOW by the OR gate when the count decrements to 000. The count stops at 000.

  19. 200 Hz Clock Input 400 Hz 100 Hz 50 Hz COUNTER USED FOR FREQUENCY DIVISION  4  8  2  16 800 Hz

  20. ? Hz 400 Hz ? Hz ? Hz 100 Hz 800 Hz USING THE 7493 COUNTER IC • Counters are available in IC form. • Either ripple (7493 IC) or synchronous (74192 IC) counters are available. 1600 Hz 7493 Counter IC wired as a 4-bit binary counter

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