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ASIC FFT Library: 8-bit Complex Multiplier

Outline. Goals

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ASIC FFT Library: 8-bit Complex Multiplier

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    1. ASIC FFT Library: 8-bit Complex Multiplier Final Design Review 12/12/2005 Team: Kevin Arruda (Lead) & Jordan Wyckoff Course : ECE 715 Name + infoName + info

    2. Outline Goals & Specifications Design Process Simulation & Design Verification Achieved Specification Project Timeline Whats Next

    3. Goals & Specifications Project definition The goal of this project is to design, simulate, and implement a functional complex multiplier to be used in creating a 16-point radix-4 FFT algorithm. ASIC using .5um technology. 100 MHz clock speed Must accommodate 2s compliment integer operands which form an 8 bit complex number. Synchronous input/output. Of Other Concern: Working Chip Efficient Design Gain insight into real-world VLSI design

    4. Design Process Research Multiplier/Adder Designs (j,k) 2s Compliment Mathematics (j,k) Physical Layout (k) Implementation Initial functional specification (j,k) Initial schematic design and implementation (j) Functionality based simulation and testing (j) Layout design (k) Determine performance capacity (j) Documentation (k)

    5. Research Complex Multiplication a, b, c, d => 4-bit 2s compliment int (a+jb)*(c+jd) = (ac + adj +bcj bd) = (ac bd) + (ad + bc)j = P v

    6. Research (cont.)

    7. Research (cont.)

    8. Research (cont.) 2s Compliment Multiplier must accommodate 2s Compliment integers. Simple binary multipliers do not. (Sign Bit) Quick Review: Binary: 111 = 4 + 2 + 1 = 7 2s Compliment: 111 = -4 + 2 + 1 = -1 The MSB always represents the sign. 0 for positive, 1 for negative. This reduces the possible range of positive numbers in exchange for the ability to represent negatives.

    9. Research (cont.)

    10. Implementation 8-bit Ripple Carry Adder

    11. Implementation 8-bit Subtractor

    12. Implementation 2s Compliment Multiplier

    13. Implementation 8-bit Complex Multiplier

    14. Simulation

    15. Simulation (cont.)

    16. Implementation II

    17. Implementation II

    18. Simulations (cont.)

    19. Simulations (cont.)

    20. Simulations (cont.)

    21. Simulation (cont.)

    22. Layout

    23. Design Results Maximum clock speed -Safe 100Mhz Chip-area Usage -W (2,361 l) x L (2,117 l) = 4998237 sq. L (l = .5um) -W (1180.5 um) x L (1058.5 um) = 1249559.25 sq. um -W ( 1.1805 mm) x L (1.0585 mm) = 1.24955925 sq. mm Power Dissapation ~ 35.6839nW / operation Slew Rate of Output -Risetime: 49.011 Ps -Falltime: 37.250 Ps Design Flaws and weaknesses? -No CLA logic -Small # of bits (albeit maximum, need more for 16-point FFT!)

    24. Project plan

    25. Whats Next? Testing of manufactured chip Comparison to rival technologies (PLDs) Hind-sight improvement ideas

    26. References & Acknowledgements

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