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Useful Things to Know

Useful Things to Know. Norm. Administrative. Midterm Grading Finished Stats on course homepage Pickup after this lab lec. Regrade requests within 1wk of posted solution Homework deadline extended to next friday. Design Flow. Description. Design Conception. Implementation.

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Useful Things to Know

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  1. Useful Things to Know Norm

  2. Administrative • Midterm Grading Finished • Stats on course homepage • Pickup after this lab lec. • Regrade requests within 1wk of posted solution • Homework deadline extended to next friday

  3. Design Flow Description Design Conception Implementation Verification (Debugging)

  4. Design Flow Description Design Conception Implementation Verification (Debugging)

  5. Classification of Elements in a Digital Circuits *Memory is an exception to the above chart. They can operate with or without clock and can store values

  6. Reminder From Lecture • Sequential, or Storage • These are the only things* that can store values. they are controlled by a clock and their output value can only change on a clock-edge. • Combinational • These cannot hold state, output is purely a function of input.

  7. Verilog… • IS a Hardware Description Laguage • Is NOT a programing language • Design your circuit first then write the code. • Was initially designed for simulating hardware • Was NOT initially designed for generating hardware • Not all “valid” verilog turns into hardware. • Some verilog turns into inefficient hardware implementation (too many CLBs…)

  8. always @ (posedge CLK or posedgea) if (a) Q <= R; else if (b) Q <= R; else if (c) Q <= D; Optional rst Q Counter en Verilog for Sequential Elements a = asynchronous set-reset line b = synchronous set-reset line R = set-reset value (should be constant) D = next value for Q (could be expression) Express any sequential logic buy substituting different values, variables for a, b, R, D a = rst, c = en, d = Q + 1; Note: it is okay to write Q <= Q…, in this case because Q is a storage element. This is not always the case.

  9. Can be written in two ways Example: 1 assign O = Y; always @ (all inputs) begin … … end Case (A) 1 : begin if (B) O <= C; end Be careful! A, B, C are all inputs! 2 Verilog for Combinational logic E • Notice: • O must be of type wire for assign statement and type reg for always statement. • However after synthesis O will physically be a wire in the circuit. I O Assign O = E ? I : 1’bZ Always @ (E or I) if (E) O <= I; else O <= 1’bZ;

  10. 1 1 A C B + + Block vs Non-blocking assign always @(posedge clk) begin c <= a+1; b <= c+1; end always @(posedge clk) begin c = a+1; b = c+1; end 1 A C + 1 B +

  11. 1 always @(A or B) begin if (A) D = B; End 2 A always @(A or B) begin if (A) D = B; else D = D; End B D Common Pitfall • Not assigning a wire outputs. (incomplete truth table therefore variable must remember previous values) • Assigning a variable to itself. (same as not assigning since reg types remembers it’s value if it is not assigned to) Template for A latch  (look familiar?) always @(GATE or DIN) begin if (GATE) DOUT = DIN; End This circuit is not combinational! Output is not just a function of inputs

  12. R C[1] A A O O B B C[0] C Tri-State or Mux? • Desired functionality • To read one of many results depending on come control information Tri-state Mux A O ? B C • Notice the tri state Has 2 control lines where as the mux has only one

  13. Xilinx 4000 CLB Structure LUTs cannot output high-impedence “Z” therefore each CLB also has a pair of Tri-states CLB 4-LUT FF 3-LUT 4-LUT FF

  14. Tri-State or Mux on Xilinx? CLB I[0] 4-LUT I[0] I[1] I[1] C[0] O 3-LUT I[2] O C[1] I[3] I[2] 4-LUT C[1:0] I[3] C[0] I[0] CLB CLB I[1] O I[2] I[3] CLB CLB C[3:0]

  15. Using Tri-states • Pros • Saves LUTS so you can use them for other things • Drives Long lines (Might be faster than other types of routing) • If you don’t use them then is just a wasted resource • Cons • Decoded select signal (make sure only one select line is high at anytime!!!) • Using up fast transmission long lines

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