Some examples

1. Lecture 9.2 Paolo PRINETTO Politecnico di Torino (Italy)University of Illinois at Chicago, IL (USA) Paolo.Prinetto@polito.it Prinetto@uic.edu www.testgroup.polito.it Some examples

2. Goal • This lecture presents some example of VHDL descriptions. • In particular, a same exercise (namely Exercise 07.08) is described and synthesized at several abstraction levels and description domains.

3. Prerequisites • Lecture 9.1

4. Homework • Students are invited to try to solve the exercises by themselves, before looking at the proposed solutions • As a further set of exercises they are invited to describe, in VHDL, the RT level combinational and sequential blocks, presented in Lecture 5.1 and 5.3, respectively.

5. Further readings • Students interested in a systematic approach to VHDL coding are invited to refer to • M. Keating, P. Bricaud: “Reuse Methodology Manual for System-on-a-Chip Designs (2nd edition),”Kluwer Academic Publisher, Norwell, MA, USA, 2000, (chapter 5, pp. 73-125)

6. 010 Exercise #07.08 • On a serial transmission line X, bits are transmitted synchronously w.r.t. a clock signal CLK, one bit per clock cycle. • A circuit to be connected to the serial line is to be designed. It samples the line X at each clock cycle. Whenever the sequence ‘010’ has been received, it asserts its output signal Z for one clock cycle. • A ‘0’ can be used, at a same time, as the last bit of a sequence and as the first bit of the next one.

7. Entity definition • library IEEE; • use IEEE.std_logic_1164.all; • entity seq_rec is • Port ( • clock, x, reset : in std_logic; • z : out std_logic • ); • end seq_rec;

8. Behavioral description system RT logic Behavioral description1 processregistered inputs behavior structure physical

9. Behavioral description1 processregistered inputs • architecture behav of seq_rec is • signal val : std_logic_vector (2 downto 0); • constant SEQUENCE : • std_logic_vector (2 downto 0):= "010"; • begin • PSO: process (reset, clock) • begin • if reset = '1' then • val <= (others =>'0'); • z <= '0';

10. Behavioral description1 processregistered inputs • architecture behav of seq_rec is • signal val : std_logic_vector (2 downto 0); • constant SEQUENCE : • std_logic_vector (2 downto 0):= "010"; • begin • PSO: process (reset, clock) • begin • if reset = '1' then • val <= (others =>'0'); • z <= '0';

11. Behavioral description1 processregistered inputs (cont’d) • elsif (clock'event and clock='1') then • val<= x & val (2 downto 1); • if (val = SEQUENCE) then • z <= '1'; • else • z <= '0'; • end if; • end if; • end process; • end behav;

12. Behavioral description1 processregistered inputs (cont’d) • elsif (clock'event and clock='1') then • val<= x & val (2 downto 1); • if (val = SEQUENCE) then • z <= '1'; • else • z <= '0'; • end if; • end if; • end process; • end behav;

13. Behavioral description1 processregistered inputs (cont’d)

14. Behavioral description1 processregistered inputs (cont’d)

15. Behavioral description1 processregistered inputs (cont’d) elsif (clock'event and clock='1') then val<= x & val (2 downto 1); if (val = SEQUENCE) then

16. Behavioral description1 processregistered inputs (cont’d)

17. Behavioral description system RT logic Behavioral description1 processnon-registered inputs behavior structure physical

18. Behavioral description1 processnon-registered inputs • architecture behav of seq_rec is • signal val : std_logic_vector (1 downto 0); • constant SEQUENCE : • std_logic_vector (2 downto 0):= "010"; • begin • PSO: process (reset, clock) • begin • if reset = '1' then • val <= (others =>'0'); • z <= '0';

19. Behavioral description1 processnon-registered inputs • architecture behav of seq_rec is • signal val : std_logic_vector (1 downto 0); • constant SEQUENCE : • std_logic_vector (2 downto 0):= "010"; • begin • PSO: process (reset, clock) • begin • if reset = '1' then • val <= (others =>'0'); • z <= '0';

20. Behavioral description1 process non- registered inputs (cont’d) • elsif (clock'event and clock='1') then • val<= x & val(1); • if ((x & val) = SEQUENCE) then • z <= '1'; • else • z <= '0'; • end if; • end if; • end process; • end behav;

21. Behavioral description1 process non- registered inputs (cont’d) • elsif (clock'event and clock='1') then • val<= x & val(1); • if ((x & val) = SEQUENCE) then • z <= '1'; • else • z <= '0'; • end if; • end if; • end process; • end behav;

22. Behavioral description1 process non- registered inputs (cont’d)

23. Behavioral description1 process non- registered inputs (cont’d)

24. Behavioral description1 process non- registered inputs (cont’d) elsif (clock'event and clock='1') then val<= x & val(1); if ((x & val) = SEQUENCE)

25. Behavioral description system RT logic Behavioral description2 process behavior structure physical

26. Behavioral description2 process • architecture behav of seq_rec is • signal val : std_logic_vector (2 downto 0); • constant SEQUENCE : • std_logic_vector (2 downto 0):= "010"; • begin • PSO: process (reset, clock) • begin • if reset ='1' then • val <= (others =>'0'); • elsif (clock'event and clock='1') then • val <= x & val (2 downto 1); • end if; • end process;

27. Behavioral description2 process • architecture behav of seq_rec is • signal val : std_logic_vector (2 downto 0); • constant SEQUENCE : • std_logic_vector (2 downto 0):= "010"; • begin • PSO: process (reset, clock) • begin • if reset ='1' then • val <= (others =>'0'); • elsif (clock'event and clock='1') then • val <= x & val (2 downto 1); • end if; • end process;

28. Behavioral description2 process(cont’d) • PO: process (val) • begin • if (val = SEQUENCE) then • z <= '1'; • else • z <= '0'; • end if; • end process; • end behav;

29. Behavioral description2 process(cont’d) • PO: process (val) • begin • if (val = SEQUENCE) then • z <= '1'; • else • z <= '0'; • end if; • end process; • end behav;

30. Behavioral description2 process(cont’d)

31. Behavioral description2 process(cont’d)

32. Behavioral description system RT logic STG behavior structure physical

33. 010 reset 1 0 R,0 0,0 0 1 0 1 0 01,0 010,1 1 Solution

34. Behavioral description system RT logic STG description2 process behavior structure physical

35. reset 1 0 R,0 0,0 0 1 0 1 0 01,0 010,1 1 STG description2 process • architecture stg of seq_rec is • type STATE_SET is (S_R,S_0,S_01,S_010); • signal state : STATE_SET; • begin • PS: process (clock, reset) • begin • if reset = '1' then • state <= S_R; • elsif (clock'event and clock = '1') then

36. reset 1 0 R,0 0,0 0 1 0 1 0 01,0 010,1 1 STG description2 process • architecture stg of seq_rec is • type STATE_SET is (S_R,S_0,S_01,S_010); • signal state : STATE_SET; • begin • PS: process (clock, reset) • begin • if reset = '1' then • state <= S_R; • elsif (clock'event and clock = '1') then

37. reset 1 0 R,0 0,0 0 1 0 1 0 01,0 010,1 1 STG description2 process(cont’d) • case state is • when S_R => • if x ='0' then • state <= S_0; • when S_0 => • if x = '1' then • state <= S_01; • end if; • when S_01 => • if x = '0'then • state <= S_010; • else • state <= S_R; • end if;

38. reset 1 0 R,0 0,0 0 1 0 1 0 01,0 010,1 1 STG description2 process(cont’d) • case state is • when S_R => • if x ='0' then • state <= S_0; • when S_0 => • if x = '1' then • state <= S_01; • end if; • when S_01 => • if x = '0'then • state <= S_010; • else • state <= S_R; • end if;

39. reset 1 0 R,0 0,0 0 1 0 1 0 01,0 010,1 1 STG description2 process(cont’d) • case state is • when S_R => • if x ='0' then • state <= S_0; • when S_0 => • if x = '1' then • state <= S_01; • end if; • when S_01 => • if x = '0'then • state <= S_010; • else • state <= S_R; • end if;

40. reset 1 0 R,0 0,0 0 1 0 1 0 01,0 010,1 1 STG description2 process(cont’d) • when s_010 => • if x = '0' then • state <= S_0; • else • state <= S_01; • end if; • end case; • end if; • end process;

41. reset 1 0 R,0 0,0 0 1 0 1 0 01,0 010,1 1 STG description2 process(cont’d) • PO: process (state) • begin • case state is • when S_010 => z <= '1'; • when others => z <= '0'; • end case; • end process; • end stg;

42. Binary encoding STG description2 process(cont’d) • architecture stg of seq_rec is • type STATE_SET is (S_R,S_0,S_01,S_010); • signal state : STATE_SET; • begin • PS: process (clock, reset) • begin • if reset = '1' then • state <= S_R; • elsif (clock'event and clock = '1') then

43. state encoding S_R 00 S_0 01 S_01 10 S_010 11 Binary encoding STG description2 process(cont’d) • architecture stg of seq_rec is • type STATE_SET is (S_R,S_0,S_01,S_010); • signal state : STATE_SET; • begin • PS: process (clock, reset) • begin • if reset = '1' then • state <= S_R; • elsif (clock'event and clock = '1') then Coded as: 0, 1, 2, 3 :

44. Binary encoding STG description2 process(cont’d)

45. One-hot encoding STG description2 process(cont’d)

46. Behavioral description system RT logic STG description1 process behavior structure physical

47. reset 1 0 R,0 0,0 0 1 0 1 0 01,0 010,1 1 STG description1 process • architecture stg of seq_rec is • type STATE_SET is (S_R,S_0,S_01,S_010); • signal state : STATE_SET; • begin • PS: process (clock, reset) • begin • if reset = '1' then • state <= S_R; • z <= '0'; • elsif (clock'event and clock = '1') then

48. reset 1 0 R,0 0,0 0 1 0 1 0 01,0 010,1 1 STG description1 process(cont’d) • case state is • when S_R => • if x ='0' then • state <= S_0; • -- z not specified, since in next state • -- it will be equal to the current one • end if; • when S_0 => • if x = '1' then • state <= S_01; • end if;

49. reset 1 0 R,0 0,0 0 1 0 1 0 01,0 010,1 1 STG description1 process(cont’d) • case state is • when S_R => • if x ='0' then • state <= S_0; • -- z not specified, since in next state • -- it will be equal to the current one • end if; • when S_0 => • if x = '1' then • state <= S_01; • end if;

50. reset 1 0 R,0 0,0 0 1 0 1 0 01,0 010,1 1 STG description1 process(cont’d) • when S_01 => • if x = '0'then • state <= S_010; • z <= '1'; • else • state <= S_R; • end if;