AIDA design review Davide Braga Steve Thomas ASIC Design Group 09 October 2008

1. AIDA design review Davide Braga Steve Thomas ASIC Design Group 09 October 2008

2. X10 stage - comparator • Comparator threshold adjustment to reduce offset • Clamping of the x10 gain stage performed by latched comparator to avoid saturation and hence big current spikes

3. Offset (Monte Carlo results) • Offset preamp: σ~0.5mV (AC coupled to shaper, does not propagate to comparator) • Offset shaper: σ~2mV • Offset x10 stage: σ~3mV • Offset comparator: σ~30mV! (~ 10 times offset previous stage!)

4. Comparator Threshold • The threshold is added to the mean value of the x10 stage output voltage. • It is generated by a selectable current (8bit) flowing in a resistor • The RC filter has a distributed reset for recovery

5. Comparator Threshold Selectable threshold: Minimum value: Vth_ min~=7mV ~=9800eV (Noise after x10gain stage expected to be σn~=3.5mV → 5σn=17.5mV)

6. Comparator Hysteresis Built-in feature (not selectable) to avoid noise on comparator output: comparator fires at: Vin>Vth+Vhyst. Vin<Vth-Vhyst. Vhyst now set to ~10mV

7. X10 gain stage clamp Most signal would saturate the x10 stage output, causing big (and long!) variations in current This can be avoided clamping the amplifier to a unity-gain configuration after the comparator has fired

8. X10 gain stage clamp - latch The comparator responsible for the clamping must be latched not to let the amplifier come back to the x10 gain configuration A timed signal will reset the latch once the signal has disappeared

9. Current stabilization Another measure has been taken to reduce current oscillation in the comparator by inserting a dummy branch which counterbalances the drop in current consumption in the device

10. Transient: false firing When the reset comes off it causes “small” activity in the shaper, which is enough to fire the comparator and also to be store on the peak hold. The comparator must be masked and the peak hold could be set in hold mode to decouple it from the shaper output Shaper Out comparator Peak Hold Resert shaper

11. Layout “left to right” channel layout, with LEC/MEC and HEC in parallel Grid distribution of power supply (“Horizontal” and “vertical”) to minimize impedence and voltage fluctuation across the chip

12. Bond-wire parasitics: C=peL/cosh-1(a/d) a=~7mm,d~25mm, L~1mm which gives C~4fF Injected charge Q=CV~12fC=75ke for single wire “Dummy” wires have opposite polarity signals. Electric field drops as r2 for a dipole, giving much lower coupling capacitance ~7mm ~2mm ~2mm

13. PADs (detail)