Download
1 / 19
220 likes | 578 Views
Device Management. OS as a resource manager Applications request services of devices Generic device manager as framework Specific device drivers plug into framework Device driver code on CPU talks to bus Messages over bus hit device controller Device controller talks to actual device.
E N D
Device Management • OS as a resource manager • Applications request services of devices • Generic device manager as framework • Specific device drivers plug into framework • Device driver code on CPU talks to bus • Messages over bus hit device controller • Device controller talks to actual device
Layers of Responsibility application Systemcalls device manager device driver messagesoverbus device controller device
Driver/Controller Conversation • CPU runs device driver code • CPU talks to controller via the bus(es) • One one level, like talking to RAM chip • Control, address, and data • Steps in telling a device to read or write • The importance of status
Programmed I/O Example • “Programmed” implies software-driven • Step 1: CPU issues request for read operation • Step 2 • device begin read operation • CPU begins polling device to see if finished • Steps 3 through n • device works on and completes read operation • CPU periodically checks device status register • Steps n+1 through n+m: CPU copies data to RAM
Interrupt-Driven I/O Example • Interrupt “informs” CPU of I/O completion • CPU has interrupt status register • checks status register at end of each instruction cycle • better than running an instruction to check status • Step 1: CPU issues request for read operation • Step 2: CPU changes tasks; I/O device begins read • Steps 3 through n: device does read operation • Step n: device sends interrupt • Step n+1: CPU changes tasks to handle interrupt • Steps n+1 through n+m: CPU copies data to RAM
Interrupt Masks • Chooses which interrupts can be serviced • Mask changes based on current situation • Mask typically enforced as AND gates to enable/disable interrupt signal
DMA Example • I/O device writes directly to RAM • CPU doesn’t have to do copy to RAM • Step 1: CPU issues request for read operation • Step 2: CPU changes tasks; I/O device begins read • Steps 3 through n: device does read operation • Steps n+1 through n+m: DMA copies data to RAM
Memory-mapped I/O • Done using chip select signal of I/O controller • I/O chips are typically grouped together • Individual chip chosen via chip select signal • Memory-mapped I/O controllers are different • Grouped with memory chips • CPU treats it like a memory chip • A memory address may not correspond to RAM • Address points to information on an I/O device
Talking to Devices • Each device has an instruction set as well • Typically device driver is a wrapper • But, how does device driver talk to device? • For SPARC, device h/w is memory-mapped • Communicate via load/store instructions • Giving device an instruction = load instruction to memory address corresponding to device instruction register • Intel CPU: in and out instructions to use bus
I/O Channels and Processors • I/O modules pack more circuitry than before • RAM chips for an I/O device • Processor for an I/O device • Now refer to channels/processors, not modules • CPU can delegate even more work • Move from simple to complex commands • Also possibility of another layer of control • Hubs and multiplexers
