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Routability Driven White Space Allocation for Fixed-Die Standard-Cell Placement

Routability Driven White Space Allocation for Fixed-Die Standard-Cell Placement. Xiaojian Yang Bo-Kyung Choi Majid Sarrafzadeh Embedded and Reconfigurable Lab Computer Science Department, UCLA. Outline. Motivation and Previous Work White Space Allocation Approach

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Routability Driven White Space Allocation for Fixed-Die Standard-Cell Placement

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  1. Routability Driven White Space Allocation for Fixed-Die Standard-Cell Placement Xiaojian Yang Bo-Kyung Choi Majid Sarrafzadeh Embedded and Reconfigurable Lab Computer Science Department, UCLA 1

  2. Outline • Motivation and Previous Work • White Space Allocation Approach • Placement with White Space • Experimental Results • Conclusion 2

  3. Motivation • Fixed-die Placement with White Space • Wirelength or Routability? Tight Placement Loose Placement Better for Wirelength/Timing Better for Routability 3

  4. Different White Space Distribution Dragon’s result without white space, Shortest Wirelength (498) unroutable 4

  5. Different White Space Distribution Dragon’s result with uniform white space, Short Wirelength (509) unroutable 5

  6. Different White Space Distribution QPlace’s result, Wirelength = 589 routable 6

  7. Different White Space Distribution Dragon’s result with congestion-driven allocation, Wirelength = 573 routable 7

  8. Previous Work • Parakh, Brown, Sakallah, “Congestion Driven Quadratic Placement”, DAC 1998 • Caldwell, Kahng, Markov, “Can Recursive Bisection Alone Produce Routable Placements?”, DAC 2000 • Industrial Placement Tools 8

  9. Our Contribution • Fast and effective white space allocation approach which does not affect the running time of the placement process • Aggressively allocating white space to maximize the effect of alleviating congestion • A study on wirelength optimization considering white space 9

  10. Allocation in Top-Down Placement • We allocate white space at finer placement level, because we have more accurate congestion map. Final Placement Allocate white Space here 10

  11. Global Placement w/o White Space 0% white space 11

  12. White Space Allocation Process Step 1: Global Placement Bins Cells White Space 13% white space 12

  13. White Space Allocation Process Step 2: Congestion Estimation 13% white space 13

  14. White Space Allocation Process Step 2: Congestion Estimation 13% white space 14

  15. White Space Allocation Process Step 3: Allocating white space 13% white space 15

  16. White Space Allocation Process Step 4: Moving cells to match the white space 13% white space 16

  17. White Space Allocation Process Step 5: Wirelength Optimization with white space 13% white space 17

  18. White Space Allocation Process Step 6: Second allocation and detailed placement 13% white space 18

  19. Allocation Based on Congestion • Congestion estimation for each bin • Cheng ICCAD’94 • Lou et al. ISPD’01 • Yang, Kastner, Sarrafzadeh ICCAD’01 • White spaces are allocated into bins according to bin congestion • First assign white space into rows, then bins 19

  20. White Space Allocation 20

  21. Aggressive Allocation • Tight placement for non-congested area, loose placement for congested area. • Depends on: • Congestion cost function • Allocation strategy Non-aggressive Aggressive 21

  22. Post Allocation Optimization • Improving wirelength using simulated annealing • Cells are swapped between bins • White spaces of bins are reserved • Variable bin width • Keep row balance in annealing: total cell width plus total white space in each row is balanced 22

  23. Experimental Setup Cadence QPlace Placed DEF IBM-PLACE2 Capo MetaPlacer Cadence WRoute LEF/DEF Dragon (Fixed-die) Allocation algorithm has been incorporated into Dragon 23

  24. Benchmarks (IBM-PLACE 2.0) • Converted from ISPD98 partitioning net-lists • New features for IBM-PLACE 2.0: • LEF/DEF and GSRC bookshelf format • Cell sizes are similar with the standard-cells in TSMC 0.18um library (from Artisan Inc.) • Aspect ratio 1.0 (arbitrary number of rows) • No space between rows • Over-the-cell routing with 4 or 5 routing layers • Exact pin locations (not center-of-cell) • Predefined core size with white space 5%-15% • Each circuit corresponds to an easy and a hard instance • Limitations • No clock/power/ground signals • No pin input/output information • No I/O pads connections 24

  25. Experimental Results Summary: Successful Finished with violations Failed 25

  26. Wirelength Comparison Overall Dragon’s results are 8.8% shorter than QPlace’s 26

  27. Runtime Comparison • Placement time: Dragon is 10-15 times slower than QPlace • Good placements significantly reduce routing time: Dragon’s placements get up to 3x speedup in routing compared with QPlace’s (on average 21% saving) • Total Place/Route time: Dragon takes 0.4-3.2 times of QPlace’s cost. (In most cases 1.5-2.5) 27

  28. Different White Space Distribution QPlace’s result, Wirelength = 590 routable 28

  29. Different White Space Distribution Dragon’s result with congestion-driven allocation, Wirelength = 579 routable 29

  30. Different White Space Distribution Capo/MetaPlacer’s result, Wirelength = 563 unroutable 30

  31. Congestion and White Space congestion map before allocation white space map for the final placement 31

  32. Conclusion & Future Work • Congestion aware white space allocation improves routability • Aggressively allocating white space helps routing in hard cases • Open problem: multiple objectives during placement 32

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