1 / 20

ELEC 7770 Advanced VLSI Design Spring 2008 Zero - Skew Clock Routing

ELEC 7770 Advanced VLSI Design Spring 2008 Zero - Skew Clock Routing. Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr08/course.html. Zero-Skew Clock Routing. FF.

matt
Download Presentation

ELEC 7770 Advanced VLSI Design Spring 2008 Zero - Skew Clock Routing

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. ELEC 7770Advanced VLSI DesignSpring 2008Zero-Skew Clock Routing Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr08/course.html ELEC 7770: Advanced VLSI Design (Agrawal)

  2. Zero-Skew Clock Routing FF FF FF FF FF FF FF FF CK FF FF FF FF FF FF FF FF ELEC 7770: Advanced VLSI Design (Agrawal)

  3. Zero-Skew: References • H-Tree • A. L. Fisher and H. T. Kung, “Synchronizing Large Systolic Arrays,” Proc. SPIE, vol. 341, pp. 44-52, May 1982. • A. Kahng, J. Cong and G. Robins, “Hig-Performance Clock Routing Based on Recursive Geomrtric Matching,” Proc. Design Automation Conf., June 1991, pp. 322-327. • M. A. B. Jackson, A. Srinivasan and E. S. Kuh, “Clock Routing for High-Performance IC’s,” Proc. Design Automation Conf., June 1990, pp. 573-579. ELEC 7770: Advanced VLSI Design (Agrawal)

  4. Zero-Skew Routing • Build clock tree bottom up: • Leaf nodes are all equal loading flip-flops. • Two zero-skew subtrees are joined to form a larger zero-skew subtree. • Entire clock tree is built recursively. • R.-S. Tsay, “An Exact Zero-Skew Clock Routing Algorithm,” IEEE Trans. CAD, vol. 12, no. 2, pp. 242-249, Feb. 1993. • J. Rubenstein, P. Penfield and M. A. Horowitz, “Signal Delay in RC Tree Networks,” IEEE Trans. CAD, vol. 2, no. 3, pp. 202-211, July 1983. ELEC 7770: Advanced VLSI Design (Agrawal)

  5. Balancing Subtrees (1) xL r1 A t1 c1/2 c1/2 C1 Subtree 1 Tapping point (1 – x)L r2 B t2 c2/2 c2/2 C2 Subtree 2 ELEC 7770: Advanced VLSI Design (Agrawal)

  6. Balancing Subtrees (2) • Subtrees 1 and 2 are each balanced (zero-skew) trees, with delays t1 and t2 to respective leaf nodes. • Total capacitances of subtrees are C1 and C2, respectively. • Connect points A and B by a minimum-length wire of length L. • Determine a tapping point x such that wire lengths xL and (1 – x)L produce zero skew. ELEC 7770: Advanced VLSI Design (Agrawal)

  7. Balancing Subtrees (3) • Use Elmore delay formula: r1(C1 + c1/2) + t1 = r2(C2 + c2/2) + t2 • Substitute: • r1 = axL, r2 = a(1 – x)L • c1 = bxL, c2 = b(1 –x)L abL2x + aL(C1+C2)x = (t2 – t1) + aL(C2+bL/2) • Then solve for x: (t2 – t1) + aL (C2 + bL/2) x = ──────────────── aL(bL + C1 + C2) ELEC 7770: Advanced VLSI Design (Agrawal)

  8. Balancing Subtrees Example 1 • Subtree parameters: • Subtree 1: t1 = 5ps, C1 = 3pF • Subtree 2: t2 = 10ps, C2 = 6pF • Interconnect: • L = 1mm • Wire parameters: a = 100Ω/cm, b = 1pF/cm • Tapping point: (t2 – t1) + aL (C2 + bL/2) (10–5) + 100×0.1(6 + 1×0.1/2) x = ──────────────── = ────────────────── aL (bL + C1 + C2) 100×0.1(1×0.1+3+6) = (5 + 60.5)/(10×9.1) = 0.7198 ELEC 7770: Advanced VLSI Design (Agrawal)

  9. Example 1 FF t1 = 5ps, C1 = 3pF FF 0.7198mm FF Subtree 1 FF To next level FF 0.2802mm t2 = 10ps, C2 = 6pF FF FF Subtree 2 ELEC 7770: Advanced VLSI Design (Agrawal)

  10. Balancing Subtrees, x > 1 • Tapping point set at root of tree with larger loading (C2, t2). • Wire to the root of other tree is elongated to provide additional delay. Wire length L found as follows: • Set x = 1 in abL2x + aL(C1+C2)x = (t2 – t1) + aL(C2+bL/2) i.e., L2 + (2C1/b)L – 2(t2 – t1)/(ab) = 0 • Wire length is given by: [(aC1)2+2ab(t2 – t1)]½ – aC1 L = ────────────────── a b • R.-S. Tsay, “An Exact Zero-Skew Clock Routing Algorithm,” IEEE Trans. CAD, vol. 12, no. 2, pp. 242-249, Feb. 1993. ELEC 7770: Advanced VLSI Design (Agrawal)

  11. Balancing Subtrees Example 2 • Subtree parameters: • Subtree 1: t1 = 2ps, C1 = 1pF • Subtree 2: t2 = 15ps, C2 = 10pF • Interconnect: • L = 1mm • Wire parameters: a = 100Ω/cm, b = 1pF/cm • Tapping point: (t2 – t1) + aL (C2 + bL/2) (15–2) + 100×0.1(10 + 1×0.1/2) x = ──────────────── = ────────────────── aL (bL + C1 + C2) 100×0.1(1×0.1+1+10) = (13 + 100.5)/(10×11.1) = 1.0225 ELEC 7770: Advanced VLSI Design (Agrawal)

  12. Example 2, x = 1.0225 Setting x = 1.0, [(aC1)2+2ab(t2 – t1)]½ – aC1 L = ────────────────── a b [(100×1)2+2100×1(15 – 2)]½ – 100×1 = ─────────────────────── 100×1 = 0.1225cm ELEC 7770: Advanced VLSI Design (Agrawal)

  13. Example 2, L = 1.255mm FF t1 = 2ps, C1 = 1pF FF FF Subtree 1 L = 1.225mm FF FF To next level t2 = 15ps, C2 = 10pF FF FF Subtree 2 ELEC 7770: Advanced VLSI Design (Agrawal)

  14. Balancing Subtrees, x < 1 • Tapping point set at root of tree with smaller loading (C1, t1). • Wire to the root of other tree is elongated to provide additional delay. Wire length L found as follows: • Set x = 0 in abL2x + aL(C1+C2)x = (t2 – t1) + aL(C2+bL/2) i.e., L2 + (2C2/b)L – 2(t1 – t2)/(ab) = 0 • Wire length is given by: [(aC2)2+2ab(t1 – t2)]½ – aC2 L = ────────────────── a b • R.-S. Tsay, “An Exact Zero-Skew Clock Routing Algorithm,” IEEE Trans. CAD, vol. 12, no. 2, pp. 242-249, Feb. 1993. ELEC 7770: Advanced VLSI Design (Agrawal)

  15. Balancing Subtrees Example 3 • Subtree parameters: • Subtree 1: t1 = 15ps, C1 = 10pF • Subtree 2: t2 = 2ps, C2 = 1pF • Interconnect: • L = 1mm • Wire parameters: a = 100Ω/cm, b = 1pF/cm • Tapping point: (t2 – t1) + aL (C2 + bL/2) (2–15) + 100×0.1(1 + 1×0.1/2) x = ──────────────── = ────────────────── aL (bL + C1 + C2) 100×0.1(1×0.1+1+10) = ( – 13 + 10.5)/(10×11.1) = – 0.0225 ELEC 7770: Advanced VLSI Design (Agrawal)

  16. Example 3, x = – 0.0225 Setting x = 0.0, [(aC2)2+2ab(t1 – t2)]½ – aC2 L = ────────────────── a b [(100×1)2+2100×1(15 – 2)]½ – 100×1 = ─────────────────────── 100×1 = 0.1225cm ELEC 7770: Advanced VLSI Design (Agrawal)

  17. Example 3, L = 1.255mm FF FF To next level t1 = 15ps, C1 = 10pF FF FF Subtree 1 L = 1.225mm FF t2 = 2ps, C2 = 1pF FF FF Subtree 2 ELEC 7770: Advanced VLSI Design (Agrawal)

  18. Zero-Skew Design Delay =75ns Delay = 50ns FF A FF B FF C Comb. Comb. CK CK time Tck = 75ns Single-cycle path delay ELEC 7770: Advanced VLSI Design (Agrawal)

  19. Nonzero-Skew Design Delay =75ns Delay = 50ns FF A FF B FF C Comb. Comb. CK Delay = 25ns CK time Tck = 50ns Single-cycle path delay ELEC 7770: Advanced VLSI Design (Agrawal)

  20. Conclusion • Zero-skew design is possible at the layout level. • Zero-skew usually results in higher clock speed. • Nonzero clock skews can improve the design with reduced hardware and/or higher speed. ELEC 7770: Advanced VLSI Design (Agrawal)

More Related