An Assembly Language Simulator to Illustrate Computer Architecture Design

1. An Assembly Language Simulator to Illustrate Computer Architecture Design Marwan Shaban, Ph.D. and Adam J. Rocke, Ph.D. Seminole State College

2. Agenda • Motivation • Solution • Existing Tools • Design Considerations • Examples • Instruction Encoding • Numeric Representation • Procedures • Future Revisions

3. Convergence College Network (CCN) • Funded by the National Convergence Technology Center (NSF Advanced Technological Education Center) • Manages the CCN community of practice featuring 64 schools in 24 states that regularly shares expertise and best practices • Engages a national Business and Industry Leadership Team (BILT) to identify needed IT job skills to keep curriculum current with industry trends • Trains faculty on emerging technologies through in-depth professional development • Developing seven regional hubs to create new relationships and boost 2+2+2 articulation pathways • Disseminates materials and processes via webinars, social media, and presentations • www.connectedtech.org

4. Motivation • Seminole State College – BS IST Program • CDA 3100 – Introduction to Computer Architecture • “This course provides an introduction to computer taxonomy, description languages, conventional computer architecture, microprogramming, instruction sets, I/O techniques, memory, survey of non-conventional architecture and software interfaces.” • New text covering the RISC-V Instruction Set Architecture (ISA). • Alternatives include MIPS and ARM. • Existing simulator tools did not meet our requirements.

5. Motivation • Teaching assembly language without a simulator is like teaching: • auto repair without cars, • music without instruments, or • swimming without water. • It is difficult to illustrate computer architecture concepts without appropriate tools. • A language simulator can illustrate these concepts and allow students to test assembly language execution.

6. Solution • Funding a solution is cost prohibitive. • In addition to being faculty, we are also practitioners. • We developed the RISC-V simulator to specifically address teaching of computer architecture and assembly language concepts. • It allows students to create and simulate the execution of programs. • This in turn facilitates understanding of internal computer operations. • We are solving a teaching problem using technology.

7. Solution

8. Solution

9. Existing Tools • Many existing tools are available: • https://github.com/riscv/riscv-wiki/wiki/RISC-V-Software-Status • FireSim - https://fires.im/ • FireSim is a cycle-accurate, FPGA-accelerated scale-out computer system simulation platform. • Imperas - http://www.imperas.com/riscv • RISC-V system emulator with library of over 200 components of Ethernet, USB, CAN, UARTs, and many other peripherals.  •  Spike - https://github.com/riscv/riscv-isa-sim • The RISC-V ISA Simulator implements a functional model of one or more RISC-V processors. • Existing tools do not meet our goals as they: • do not visually update memory and registers in real time, • operate via the command-line, • focus on simulating multiple nodes, and • many are unmaintained.

10. Educational vs. Industrial Software • Industrial tools often have too many features. • May be inappropriate for classroom use. • Difficult and time consuming to learn. • Educational software can be more user friendly. • Goal: make the experience fun and encourage student engagement. • Educational focus allowed us to leave out certain features. •  Omit uncommon instructions. •  Do not need memory segmentation common in other assemblers. • The result is a reduced development time and simpler end product.

11. Design Considerations • Focus on education. •  Design for usability. •  Release as open source to encourage collaboration. • Implement the simulator using cross-platform and free components. •  Use QT as the application framework. • The simulator should be fast, portable, and extensible. •  The simulator is written in C++.

12. Simulator Feature List • Register array and memory update in real time. • Set breakpoints and step through programs one instruction at a time. • "Explain Instruction". • Instruction format, encoding, and binary values shown for all instructions. • Faithful implementation of the RISC-V architecture, for instance: • two's compliment signed integer representation and the • IEEE 754 format for floating point numbers. • Implement the most important instructions. • Instructions such as doubleword variants are not currently implemented.

13. Additional Simulator Features • Support for labels and breakpoints. • Some pseudo-instructions, such as J, MV, NOP, are implemented. • Enable basic input and output functions. • Assemble instructions in real-time. • Support constant data. • The simulator currently runs on Windows, macOS and Linux.

14. RISC-V Instruction Set • Supported • Base integer RV32I, except • Some doubleword variants • Sync, System, Counters, LDU • Optional mul-div, except • Doubleword variants • Upper half instructions • Some optional floating point • Load, store, convert, arithmetic, compare • Not supported • RV privileged • Optional 16-bit extension • Optional atomic extension • Supported • Base integer RV32I, except • Some doubleword variants • Sync, System, Counters, LDU • Optional mul-div, except • Doubleword variants • Upper half instructions • Some optional floating point • Load, store, convert, arithmetic, compare • Not supported • RV privileged • Optional 16-bit extension • Optional atomic extension

15. Demonstration • Create new program. • Execute instructions.  • Registers and memory update in real time. • Program is assembled as it is being edited. • Load an existing program. • Demonstrate pseudo-instructions such as j and mv. • Input-output example. • Other samples to demonstrate functionality are available.

16. Example – Instruction Encoding • Question: • Provide the type and assembly language instruction for the following hex values: • Address 1000: b3 • Address 1001: 0b • Address 1002: 9c • Address 1003: 41 • Hint: consider big-endian vs. little-endian, convert to binary, divide the bits into fields, and decipher the opcode. • Answer: • 0100000  11001  11000  000  10111  0110011 • funct7       rs2       rs1    funct3    rd     opcode • sub x23, x24, x25 \\ R-format

17. Example – Instruction Encoding

18. Example – Numeric Representation positive: data 1024015 negative: data –12 pi: data 3.14159 one_point_one: data 1.1

19. Example – Two’s Complement

20. Example – IEEE 754 Floating Point

21. Example – Procedures • Adapted from “Computer Organization and Design”, RISC-V Edition, Patterson and Hennessy, Pages 98 – 102. • Given the statement: f = ( g + h ) – ( i + j ) • Written as a C language procedure: long long int leaf_example (long long int g, long long int h, long long int I, long long int j) { long long int f; f = ( g + h ) - ( i + j ); return f; } • What is the compiled RISC-V assembly code?

22. Example – Procedures • RISC-V version: addi x10, x0, 10 //g addi x11, x0, 11 //h addi x12, x0, 12 //i addi x13, x0, 13 //j addi x5, x0, 5 addi x6, x0, 6 addi x20, x0, 20 addi x2, x0, 2040 // sp is stored in register x2

23. Example – Procedures jal x1, leaf_example addi x8, x0, 8 leaf_example: addi x2,x2,-24 sd x5,16(x2) sd x6,8(x2) sd x20,0(x2) add x5,x10,x11 add x6,x12,x13 sub x20,x5,x6 addi x10,x20,0 ld x20,0(x2) ld x6,8(x2) ld x5,16(x2) addi x2,x2,24 jalr x0,x1, 0

24. Example – Procedures

25. Student Response • First used in the classroom in the Spring 2018 semester. • Initial reviews are favorable. • Provides a hands-on component to the course. • Enhances learning. • Fun and engaging for the students. • Student have requested new features. • Add a “reset button”. • Provide a way to enter values directly.

26. Future Development • Add usability enhancements such as automatic resizing of windows. • Preserve the PC location after a user edits the program. • Add functionality to directly modify registers and memory.

27. Simulator Download • The simulator can be used in various courses including: • computer architecture, • assembly language programming, • or general programming. • GitHub repository: • https://github.com/ProfessorShaban/risc-v-simulator.git • Build using QT Creator

28. Questions and Contact Information • Professor Marwan Shaban, Ph.D. • shabanm@seminolestate.edu • Professor Adam J. Rocke, Ph.D. • rockea@seminolestate.edu