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Outline. MOSFET Basics Ideal MOSFET physics Main parameters : threshold, leakage and speed What MOSFET for what application ? Scaling theory and good design rules of CMOS Devices The Real World Threshold voltage control limitations Gate oxide leakage and capacitance scaling

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  1. Outline • MOSFET Basics • Ideal MOSFET physics • Main parameters : threshold, leakage and speed • What MOSFET for what application ? • Scaling theory and good design rules of CMOS Devices • The Real World • Threshold voltage control limitations • Gate oxide leakage and capacitance scaling • Technological Solution ? • Gate alternative : High-K and Metal Gate • Channel engineering : Strained-Si • Alternative devices and substrates • Basic logic functions

  2. MOSFET Basics

  3. Making a Switch with Metal, Oxide and Silicon E Energy Barrier C = S D Carrier reservoir Source Drain x Vg Energy Barrier 0 Metal Carrier reservoir Oxide Source n+ n+ Si (p) Drain x Vd

  4. VG=0V VG>0V What is an ideal MOS Transistor ? G G VS=0V VD>0V VS=0V + + + + + + VD>0V D D S S - - - - - - - IDS Canal vide : courant nul Canal rempli : courant non nul A TMOS bloqué B TMOS passant A MOS capacitor is modulating the transport between two carrier reservoir ON-STATE OFF-STATE MOS capacitance : Field Effect  MOSFET

  5. n-type & p-type MOSFETs Vg<0 Vd>0 Vd<0 0 Metal Oxide p+ p+ Si (n) Vg>0 0 Metal Oxide n+ n+ Si (p) nMOSFET Electron conduction pMOSFET Hole conduction

  6. MOSFET morphology Gate (Poly-Si) Métal Oxyde Semi- conducteur Si Source Drain

  7. Basic Physics of MOSFET ON state Current OFF state Current OFF State Current (Thermal) Threshold (Vth) Log(Idrain) MOSFET switch Ideal switch • 3 main parameters • Threshold Voltage • Ion (=speed) • Ioff (=stand-by power) Vgate

  8. MOSFET Physics L nMOSFET VG=0 L VG=VD gate grille channel L VD VS L VD source drain VS Tox - - - - - canal source drain - - - Tox N N P - - - - - - + + + + N N P + + + WD/C + + WS/C P WD/C WS/C P - - - - - - - - - N - - - - - VB - BC d - - - - - - N N N VD BC VB « Off State» - - -

  9. Threshold Voltage (Vth) L gate Channel Doping channel source drain WD/C WS/C P - - - - - - - - - Oxide Thickness N Gate Material BC N VD - - -

  10. On State Current (Ion) Vg-Vth Vg-Vth-VDS Gate Lgate Source Drain L

  11. Off – State Current (Ioff) VG1<Vth VG1<VG2<Vth Ithermique Idiffusion Ithermique Idiffusion VD>0 VD>0 Log Idrain - - - - - - - - - - - - + dec Ioff 1/S Vth Vgate Modulation of barrier heigth by Capacitive coupling S should be as small as possible

  12. The Static Leakage Components i) Gate leakage (oxide thickness dependance) Ioff = IS + IG + IB ii) Channel Leakage (Vth and S dependant) iii) Junction leakage (doping dependance)

  13. CMOS Scaling CMOS032 CMOS045 CMOS065 CMOS090 CMOS120

  14. Scaling Theory: Moore’s law • Gordon Moore, a co-founder of Intel said in 1965: • “Component count per unit area doubles every two years” • Last 40 years : technological advances achieved mainly by reducing • transistors size • - However current trend of miniaturization causes undesired effects degrading the electrical parameters and transistor performance • In reality: • µ decreases • Tox levels-off • Off current increases as transistor size is reduced

  15. Ideal MOSFET Basics summary • Threshold Voltage : • Determines the gate voltage transition Vth between Off-state and On-state regimes • Vth depends (at the 1st order) on the channel doping and gate electrode material • On-State : • MOS gate capacitance lowers channel barrier • electrons(holes) flow from Source to Drain Ion current • Carrier transit time is Cgate*Vgate / Ion the higher Ion the faster the device • Off-State : • MOS gate capacitance potential = 0 • electrons(holes) flow from Source to Drain due to Thermionic current Ioff current • Static Power dissipation is Pstat = VDS * Ioff

  16. Part 2. The Real World

  17. Vth Control : Short Channel Effects Zone de charge d’espace ZCE Log Idrain SCE DIBL SCE DIBL BC VDS SCE=Short Channel Effect Vth Vth2 Vth1 DIBL=Drain Induced Barrier Lowering Vgate L

  18. MOSFET Typical Lenghts and Ratios Lgate,phys Tox gate source drain Tdep Xj Lel Good design rules of MOSFET architecture : T T V X 1 ox 1 1 1 j dep th » » » » ; ; L 3040 L 3 L V 3 5 el el el dd

  19. Scalingrules (MASTAR Model) VTH(short Mosfet)=VTH(long)-SCE-DIBL æ ö 2 X T T e ç ÷ j dep ox Si = + 0.8 SCE 1 V ç ÷ bi e 2 L L ç ÷ L ox el el è ø el æ ö 2 X T e ç ÷ T j dep ox Si = + 0.8 DIBL 1 V ç ÷ ds e 2 L L ç ÷ L ox el el è ø el 1 Wel = m I C (V V -Vth) dsat eff ox g dsat 2 Lel T. Skotnicki et al. IEEE EDL, March’88 & IEDM’1994

  20. Why is it so difficult to get a « Good Scaling » ? Lgate,phys gate source drain Tdep Xj Lel Oxide Scaling Junction Scaling Doping increase Subthreshold control

  21. Tox/Lel ratio : Gate Oxide Scaling Lgate,phys Poly-Si gate source drain Tdep Xj Lel zz zz

  22. The Gate-Poly Silicon Depletion 20 20 NMOS ( NMOS ( Npoly Npoly =1e20cm =1e20cm - - 3) 3) , A , A 18 18 Tp Tp Tp (EOT) (EOT) (EOT) Vdd scaled 16 16 @ @ @ with Tox 14 14 1.8V 1.8V 1.8V polydepletion polydepletion 1.3V 1.3V 1.3V 12 12 1.0V 1.0V 1.0V 10 10 0.7V 0.7V 0.7V 0.5V 0.5V 0.5V 8 8 0.35V 0.35V 0.35V 6 6 0.25V 0.25V 0.25V EOT of EOT of 4 4 2 2 0 0 0 0 10 10 20 20 30 30 40 40 CMOS relevant CMOS relevant Tox Tox , A , A N+ P+ Tdeppoly = 0.4nm 0.6nm Ref.: E. Josse et al., IEDM’99

  23. The problem of Gate Leakage Poly-Si Ec Ef Ev Ef Ec Ev Substrate Si P Gate N+ Si SiO2 Wpd 2 2A reduction in Tox ~ 1 dec increase in gate leakage

  24. Impact of Gate Leakage on Circuits 0 1 1 0 0 0 Igoff Ioffcanal 0 0 If Tox , Ig , Power IgOn In Static Mode, two gate leakages: IgOff & IgOn : increase of Ioff

  25. Vth/Vdd Ratio Log(I ) DS I off V V gs th If Vdd drops, just decrease the Vth too keep a good Ion. But … S degrades at smaller L !

  26. What Did We Learn ? Junc. Leak. Ioff (power) increase Rs increase Ion (speed) reduction Gate leakage Higher Ioff Darkspace Limited Scaling Ion reduction Ion reduction Polydepletion Controlling Vth (Ioff) Increasing Doping Scaling Jonctions Scaling Tox ReducingVdd (power)

  27. Technological Boosters to recover a HealthyScaling

  28. Whatcanwe do to retrieve a HealthyScaling ? Gate Source Drain NiSi NiSi Silicon channel Oxide Scaling Junction Scaling Low RSD for lower Xj Better Contact Resistance Less Gate Lekage No Poly Depletion Subthreshold control Vs Overdrive Doping increase Better Ion at the same overdrive Better Subthreshold Slope DIBL-Free Architecture

  29. MobilityEnhancement

  30. Ion Enhancement by materials Transistor Architecture Material Properties Velocity saturation regime Velocity Carrier velocity under electric field E in the linear regime: v = µ E µ Ecritical Efield

  31. Mobility In Silicon 2 E = c v * m 2. High t (less possible collision) • Small m* : ligth electrons or holes t = µ q * m E Shockwave from lattice vibration, or impurities, or gate oxide rugosity every t seconds carrier, mass m* Effective mass of carrier Linked to valence/conduction bands

  32. Gate Capacitance Scaling : High-K dielectrics

  33. Figthing against Gate Leakage Ec Ef Ev Ef Ec Ev Substrate Si P Gate N+ SiO2 Wpd Reducing Tunneling… Increasing Tox ! But without reduction of Cox ! Increasing permitivity  HIGH K materials Leakage issue Polydepletion issue Replacing Poly-Si by Metal

  34. Context Figthing against Gate Leakage • Down to 90nm gate length,N+ and P+ polysilicon gate was used for CMOS integration compatible with oxide or oxynitride gate dielectric. • Due to aggressive scaling of the gate dielectric, the gate leakage is becoming unacceptably high (>Ioff), requiring the use of high-k dielectric • Due to the incompatibility of polysilicon gate with high-k dielectric (Fermi pinning, large Vt, mobility degradation) and the need to boost performance (elimination of polydepletion, boron penetration,…), metal gate electrodes will likely be needed • For bulk technology, two metals with WFs close to the bandgap edges are needed (high channel doping required to control SCE). • For FDSOI or double gate devices, WFs within 250meV from midgap are preferred, requiring more complex integration • Two integration approaches are considered: gate first and gate last.

  35. High-k dielectric 100 FD SOI nMOS, Vg = 1.1V Exp data. 10 MASTAR 2 Dec 1 Poly-Si/SiON 1 Dec 0,1 JgON (A/Cm²) 0,01 MG/SiON 0,001 2 Dec 0,0001 MG/Hf SiON MG/HfO2 0,00001 17 19 21 23 25 27 CET (A) • For EOTs below 20Å, gate leakage current becomes higher than off-state leakage current. High-k dielectric • High-k (HfO2, ZrO2, Hf-based or Zr-based, LaO2, Al2O3,… ALCVD or MOCVD deposition • Pre-deposition clean and post deposition anneals affect the quality of high-k • Large Vt: Fermi pinning at the poly-Si/ Metal oxide interface but occurs also metal gate electrodes C. Fenouillet et al IEDM 2007 Compatibility of polysilicon gate with high-k is unlikely ! • High-K  At an equivalent CET of SiON dielectric, the gate leakage current is reduced by more than 2 decades

  36. High-k Dielectric : Issues • Mobility degradation - Many publications have reported mobility degradation using high-k dielectrics. • Possible cause is coupling of soft optical phonons in high-k with inversion channel charge carrier • Vt instabilities and reliability and noise issues • Large k and large dielectric thickness result in fringing field (FIBL) and loss of control of the channel by the gate B. Tavel et al, PhD Thesis 2002

  37. Gate Capacitance Scaling : Metal Gates

  38. Choosing The « Good Metal » nMOS Gate poly-Si N+ Metal Gate « N+like » Ec Mid-gap Gate 1.12V Ev pMOS Gate poly-Si P+ Metal Gate « P+like »

  39. Metal gate integration • The use of metal gate suppress: • the polysilicon depletion : a reduced CET of 3-5Å for performance improvement • and suppress the boron penetration problem • Two approaches have been proposed: gate first or gate last • Gate first approach requires to take care of FE contamination tool, metal etching and to the high temperature anneal • Gate last approach (replacement gate): dummy gate removal and replacement, gate dielectric integrity has to be kept But for some applications CMOS requires 2 different metal gates in order to separate WFs for NMOS and PMOS devices (Dual metal gate integration)

  40. Why is Metal Workfunction so important ? Regular Poly-gate n+/p+ Dual n+/p+ Metal Gate Mid-gap Metal Gate Log Id Log Id Log Id +0.5V +0.5V Vth,p Vth,p Vth,n Vth,n Vth,p Vth,n Vg Vg Vg +25% Polydep reduction Id Id Id Ion,n Ion,p Ion,n Ion,p Ion,p Ion,n Vg Vg Vg Vdd Vdd Vdd Vdd Vdd Vdd

  41. Metal gate interest for FDSOI • Why midgap metal gate ? • Midgap electrode with undoped channel : symmetrical Vth for NMOS and PMOS for high Vth applications • With Band edge gate electrodes (as poly-Si), FDSOI requires very high channel doping > 8e18 at/cm3 for HVT -> Variability degradation • Why high-k ?

  42. Device Architecture

  43. Device Architecture GP FD SON Bulk Xj Tdep DG (Delta, FinFET, SON, Vertical, TriGate, Omega, etc., etc. PD SOI FD SOI Scalability ? Scalability as BULK Scalability may be better or worse (GP,BOX) Scalability very much improved Scalability much improved if GP REF.:T. Skotnicki, invited paper ESSDERC 2000, pp. 19-33, edit. Frontier Group

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