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Flip-Flops

Flip-Flops. Basic concepts. Flip-Flops. A flip-flop is a bi-stable device: a circuit having 2 stable conditions (0 or 1) 3 classes of flip-flops latches: outputs respond immediately while enabled (no timing control) pulse-triggered flip-flops: outputs response to the triggering pulse

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Flip-Flops

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  1. Flip-Flops Basic concepts

  2. Flip-Flops • A flip-flop is a bi-stable device: a circuit having 2 stable conditions (0 or 1) • 3 classes of flip-flops • latches: outputs respond immediately while enabled (no timing control) • pulse-triggered flip-flops: outputs response to the triggering pulse • edge-triggered flip-flops: outputs responses to the control input edge A. Yaicharoen

  3. Conventions • The circuit is set means output = 1 • The circuit is reset means output = 0 • Flip-flops have two output Q and Q’ or (Q and Q) • Due to time related characteristic of the flip-flop, Q and Q’ (or Q) are usually represented as followed: • Qt or Q: present state • Qt+1 or Q+: next state A. Yaicharoen

  4. 4 Types of Flip-Flops SR flip-flop JK flip-flop D flip-flop T flip-flop A. Yaicharoen

  5. SR Latch An SR (or set-reset) latch consists of • S (set) input: set the circuit • R (reset) input: reset the circuit • Q and Q’ output: output of the SR latch in normal and complement form Application example: a switch debouncer A. Yaicharoen

  6. SR latch A. Yaicharoen

  7. An application of the SR latch Effects of contact bounce. A switch debouncer. A. Yaicharoen

  8. latch A. Yaicharoen

  9. Gated SR latch (c) A. Yaicharoen

  10. Gated D latch A. Yaicharoen

  11. Timing Consideration When using a real flip-flop, the following information is needed to be considered: • propagation delay (tpLH, tpHL) - time needed for an input signal to produce an output signal • minimum pulse width (tw(min)) - minimum amount of time a signal must be applied • setup and hold time (tsu, th) - minimum time the input signal must be held fixed before and after the latching action A. Yaicharoen

  12. Propagation delays in an SR latch A. Yaicharoen

  13. Timing diagram for an SR latch A. Yaicharoen

  14. Minimum pulse width constraint A. Yaicharoen

  15. Timing diagram for a gated D latch A. Yaicharoen

  16. Unpredictable response in a gated D latch A. Yaicharoen

  17. Master-slave SR flip-flop A. Yaicharoen

  18. Timing diagram for a master-slave SR flip-flop A. Yaicharoen

  19. Master-slave JK flip-flop A. Yaicharoen

  20. Timing diagram for master-slave JK flip-flop A. Yaicharoen

  21. Master-slave D flip-flop A. Yaicharoen

  22. Master-slave T flip-flop A. Yaicharoen

  23. Positive-edge-triggered D flip-flop A. Yaicharoen

  24. Timing diagram for a positive-edge-triggered D flip-flop A. Yaicharoen

  25. Negative-edge-triggered D flip-flop A. Yaicharoen

  26. Asynchronous Inputs • do not require the presence of a control signal • preset (PR) - set the flip-flop • clear (CLR) - reset the flip-flop • useful to bring a flip-flop to a desired initial state A. Yaicharoen

  27. Positive-edge-triggered D flip-flop with asynchronous inputs A. Yaicharoen

  28. Positive-edge-triggered JK flip-flop A. Yaicharoen

  29. Positive-edge-triggered T flip-flop A. Yaicharoen

  30. Master-slave JK flip-flop with data lockout A. Yaicharoen

  31. Characteristic Equations • algebraic descriptions of the next-state table of a flip-flop • constructing from the Karnaugh map for Qt+1 in terms of the present state and input A. Yaicharoen

  32. Characteristic equations A. Yaicharoen

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