Optimizing Analog Bandwidth and Signal-to-Noise for Timing Resolution

1. Stefan Ritt Paul Scherrer Institute The role of analog bandwidth and signal-to-noise in timing for waveform digitizing Timing Workshop, Chicago

2. Timing measurement How can we measure timing in an optimal system? Timing Workshop, Chicago

3. The ideal digitized signal • No noise • Always same height • Derive time from thresholdcrossing with interpolation Threshold Timing determined by “aperture jitter” Timing Workshop, Chicago

4. Aperture jitter Flash ADC Switched CapacitorArray Datasheet AD9222 (Analog Devices) PLL • Determined by write switch jitterplus inverter jitter • Measurements indicate typicalvalue 2-5 ps for current designs • Data sheet: <1ps • Measured indirectly thoughside-band of sine signal • AD Application Note AN501:50fs (clk) + 190fs (ADC) Timing Workshop, Chicago

5. Aperture jitter of clock distribution Timing Workshop, Chicago

6. The varying digitized signal • Signals with different amplitudetrigger at different times(“time walk”) Upper threshold Lower threshold • Time walk correction • Multi-level threshold • Constant-fraction discrimination J.-F. Genat et al., arXiv:0810.5590 (2008) Timing Workshop, Chicago

7. Effects of analog BW How does the analog bandwidth affect the timing ? Timing Workshop, Chicago

8. Realistic signal with noise Effect of rise time Noise affects timing! voltage noise band of signal timing jitter arising from voltage noise Noise Timing timing jitter is much smaller for faster rise-time Timing Workshop, Chicago

9. Nyquist-Shannon Theorem If a function x(t) contains no frequencies higher than F Hertz, it is completely determinedby giving its ordinates at a series of points spaced 1/2F seconds apart. Nyquist-Shannon fulfilled Nyquist-Shannon not fulfilled • If a detector produces frequencies up to 500 MHz (0.6 ns rise time), all information from that detector is recorded if sampled at 1 GSPS with good enough signal-to-noise (SNR) ratio • Sampling speed above Nyquist adds redundant points which improve the SNR

10. Does higher sampling speed help? = • Higher sampling speed adds only redundant points if Nyquist is fulfilled • If noise comes from chip → reduce noise √2 • Equivalent to double sampling of points PSI,

11. How is timing resolution affected? voltage noise Du signal height U timing uncertainty Dt rise time tr Simplified estimation! number of samples on slope Timing Workshop, Chicago

12. How is timing resolution affected? Assumes zeroaperture jitter today: optimized SNR: next generation: next generation optimized SNR: How to achieve this? includes detector noise in the frequency region of the rise time and aperture jitter Timing Workshop, Chicago

13. Effect of S/N • S/N ratio goes linearly into timing resolution! • Analog BW and sampling speed will soon hit some “hard” limits (3-5 GHz, ~20 GSPS) • Preamplifier makes sense if detector noise is smaller than SCA internal noise • In the end, higher timing resolution will be the battle of noise→ Eric’s talk tomorrow PCB SCA f ADC Det. Timing Workshop, Chicago

14. What limits the BW? Which are the crucial points in the signal chain? Timing Workshop, Chicago

15. Detector (covered in next talks) Connector (LEMO connector has a BW of ∼500 MHz) Cable (RG58: 5 m has a -3db BW of 1 GHz) PCB Preamplifier Chip package On-chip bus Analog cell switch Storage capacitor Signal Chain PCB Chip Det. Cpar Timing Workshop, Chicago

16. Amplifier 750 MHz ∼40pF Cpar Timing Workshop, Chicago

17. Effects from the chip → Tomorrow’s talk Timing Workshop, Chicago

18. Conclusions Optimize BW of detector Optimize BW of transmission Optimize S/N for digitization Fit digitization B/W to signal Fulfill Nyquist-Shannon Timing Workshop, Chicago