1 / 30

ARM Processor: Core Data Flow Model and Exceptions

Understand ARM Core Data Flow Model, Registers, Program Status Register, Pipeline, Exceptions, and Core Extensions in ARM architecture revision. Learn about the 37 registers, PSR, CPSR, SPSR, instruction handling, cache, TCM, MPU, MMU, and coprocessors.

mohler
Download Presentation

ARM Processor: Core Data Flow Model and Exceptions

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. ARM Processor www.clabsys.com

  2. Agenda • ARM Core Data Flow Model • Registers • Program Status Register • Pipeline • Exceptions • Core Extensions • ARM Architecture Revision

  3. ARM Core Data Flow Model

  4. Registers • ARM has 37 registers which are 32-bits long • Program counter : 1 • CPSR : 1 • SPSR : 5 • General purpose registers : 30 • The current processor mode governs which of several banks is accessible

  5. ARM Register Set

  6. Program Status Register (PSR) • CPSR holds the current status information • SPSR preserves the CPSR during exceptions

  7. PSR : Condition Flags • N : Negative result from ALU • Z : Zero result from ALU • C : ALU operation Carried out • V : ALU operation overflowed • Q : Overflow & Saturation • ARMv5TEJ only

  8. PSR : Processor States

  9. PSR : Interrupt Masks • used to stop specific interrupt requests from interrupting the processor • I = 1: • Disables the IRQ • F = 1: • Disables the FIQ

  10. PSR : Processor Mode

  11. Pipeline • The mechanism a RISC processor uses to execute instructions

  12. Exceptions • Reset • When power is applied • Undefined instruction • When the processor cannot decode an instruction • Software interrupt • When the processor meet an SWI instruction

  13. Exceptions (Cont.) • Prefetch abort • When the processor attempts to fetch an instruction from an address without the correct access permission • Data abort • When an instruction attempts to access data memory without the correct access permissions

  14. Exceptions (Cont.) • Interrupt request (IRQ) • When an external hardware interrupts the normal execution flow of the processor • Fast interrupt request (FIQ) • When an hardware requiring faster response times interrupts the normal execution flow of the processor

  15. Exception vector table

  16. Exception handling • When an exception occurs, • Copies CPSR into SPSR_<mode> • Sets appropriate CPSR bits • Change to ARM state • Change to exception mode • Disable interrupts (if appropriate) • Stores the return address in LR_<mode> • Set PC to vector address

  17. Exception handling (Cont.) • To return, • Restore CPSR from SPSR_<mode> • Restore PC from LR_<mode>

  18. Core Extensions • Cache • TCM (Tight Coupled Memory) • Memory Management Hardware • Non-protected Memory • MPU (Memory Protection Unit) • MMU (Memory Management Unit) • Coprocessors

  19. Cache • Improves the overall system performance < A simplified Von-Neumann architecture with cache >

  20. TCM • Improves deterministic real-time response < A simplified Harvard architecture with TCMs >

  21. Memory Management Hardware • Non-protected memory • Small embedded systems that require no protection from rouge application • MPU • Simple systems that uses a limited number of memory regions • MMU • More sophisticated platform operating systems that support multitasking

  22. Coprocessors • Extends the processing features of a core by extending the instruction set or by providing configuration registers • Vector Floating-Point (VFP) operations • CP10/CP11 • System Control Coprocessor • CP15 • Controls the cache, TCMs, MPU, MMU

  23. ARM Architecture Revision • ARM {x}{y}{z}{T}{D}{M}{I}{E}{J}{F}{-S} • ARM7/ARM9/ARM10/ARM11 • ARM7TDMI/ARM720T/ARM7EJ-S • ARM920T/ARM922T/ARM940T • ARM926EJ-S/ARM946E-S/ARM966E-S • ARM1020E/ARM1020E/ARM1022E • ARM1136J-S/ARM1136JF-S

  24. ARM7 • Von Neumann architecture • Unified cache • Both data and instructions use the same bus • 3-stage pipeline • ARMv4T • Example • ARM7TDMI • ARM720T • ARM7EJ-S

  25. ARM7 (Cont.)

  26. ARM9 • Harvard architecture • Saperated Instruction memory interface • Data memory interface • 5 stage pipeline • Example • ARM920T/ARM922T • ARM940T • ARM946E-S/ARM966E-S • ARM920EJ-S

  27. ARM9 (Cont.)

  28. ARM10 • 6 stage pipeline • Vector Floating-Point • Example • ARM1020E • Separate 32K D+I caches • VFP/MMU • Dual 64-bit bus interface • ARM1026EJ-S • Both MPU and MMU

  29. ARM11 • 8-stage pipeline • ARMv6 • SIMD (Single Instruction Multiple Data) • Example • ARM1136J-S • ARM1136JF-S

  30. StrongARM/Xscale • Harvard architecture • separate D+I caches • 5-stage pipeline • Not support the Thumb instruction set

More Related