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Example of Scheduling and Allocation

Example of Scheduling and Allocation. based on Jaap Hofstede. IIR Filter. #define m1 … #define m2 … #define m3 … #define m4 … main() { float t, i1, o1, d1=0.0, d2=0.0; while (1) { in(i1); t = i1 + m3*d2 + m1*d1; o1 = t + m4*d2 + m2*d1; d2 = d1; d1 = t; out(o1); } }.

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Example of Scheduling and Allocation

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  1. Example of Scheduling and Allocation based on Jaap Hofstede IIR Filter

  2. #define m1 … #define m2 … #define m3 … #define m4 … main() { float t, i1, o1, d1=0.0, d2=0.0; while (1) { in(i1); t = i1 + m3*d2 + m1*d1; o1 = t + m4*d2 + m2*d1; d2 = d1; d1 = t; out(o1); } } Specification in C Recursive circuit IIR Filter with 4 coefficients

  3. Memory elements Draw data flowgraph Original dataflow graph

  4. #define m1 … #define m2 … #define m3 … #define m4 … main() { float t, i1, o1, d1=0.0, d2=0.0; while (1) { in(i1); t = i1 + m3*d2 + m1*d1; o1 = t + m4*d2 + m2*d1; d2 = d1; d1 = t; out(o1); } } Please note the feedback loop in this circuit t This is example of wide class of circuits called linear systems with applications in communication, image processing, radar, control, robotics, prediction etc . See 573 class

  5. ASAP D1 D2 m1 m3 m2 m4 :=     C4 C3 C6 C5 i1 + + C1 C7 + C2 input + C8 output D2 D1 o1 ASAP (4 stages) Feedback not shown Calculate multipliers and adders with students

  6. ALAP D1 D2 m3  C3 m1 m2 m4 i1  +   C4 C1 C6 C5 := + + C2 C7 + C8 D2 D1 o1 ALAP (4stages) Calculate multipliers and adders with students

  7. Move operators D1 D2 m3  C3 Calculate multipliers and adders with students m1 i1  + C4 C1 + m2  C2 C6 m4 :=  ??in adder C5 + C7 + 1 Adder, 1 multiplier (6 stages - tradeoff) C8 D2 D1 o1

  8. Move operators D1 D2 m3  C3 m1  C4 i1 + m2  C1 C6 m4 := +  C2 C5 + C7 + 1 Adder, 1 multiplier (6 stages)C1, C2 moved down C8 D2 D1 o1

  9. Move operators, create pipeline, look at c3 c4 D1 N2 N1 D2 i1 + m2  C1 C6 1 m4 +  := C2 C5 2 m3 +  C7 3 C3 m1  + 1 Adder, 1 multiplier (4 stages)loop pipeline C4 C8 4 D2 N1 N2 D1 o1

  10. There are many methods to add registers. Here we take into account feedbacks that are not shown. We assume the same delay for add and mul. Separate logic blocks with one register Add pipeline registers N1 D1 N2 D2 v5 and v6 are compatible i1 + m2  C1 C6 1 V1 V2 m4 +  := C2 C5 2 V5 V3 V4 m3 +  C7 C3 V6 V7 m1  + C4 C8 V8 V9 9 Registers included N1 D2 N2 D1 o1

  11. V1 created in time 1 Time steps 1 2 3 4 V1 V1 used in time 2 and not used after V2 V3 V4 V5 v5 and v6 are compatible V6 V7 V8 V9 V3 created in time 2 Analyze Lifetimes of registers 9 Registers included

  12. Find registers that are compatible, their cliques v5 and v6 are compatible compatible 3:= 5 1+ 4+ 8 7+ 2 6 9+ We can prove from this graph that creating a clique 5,7,8 would not lead to smaller number of registers Ri Lifetime compatibility graph(+  := is source of data)

  13. R4 R2 R1 3 5 1 R5 4 8 7 2 6 R6 9 R3 Clique partitioning

  14. I1 I1 R3 m2 R5 R2 R1 m4 R4 R3 R1 m3 R4 R5 R2 m1 R5 Numbers are time steps 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 Correspondingnon-optimiseddata path +  Numbers are time steps 1,3 4 2 2 2,4 1,3 R3 R2 R6 R5 R4 R1 R2 O1 R5 R4 R1 R3

  15. N1 D1 N2 D2 i1 + m2  C1 C6 1 V1 V2 m4 +  := C2 C5 2 V5 V3 V4 m3 +  C7 C3 V6 V7 m1  + C4 C8 V8 V9 N1 D2 N2 D1 o1

  16. N1 D1 N2 D2 i1 + m2  C1 C6 Step 1 V1 V2 m4 +  := C2 C5 2 Step 2 V5 V3 V4 m3 +  C7 C3 Step 3 V6 V7 m1  + C4 C8 Step 4 V8 V9 N1 N2 D1 o1 D2 I1 I1 R3 m2 R5 R2 R1 m4 R4 R3 R1 m3 R4 R5 R2 m1 R5 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 Correspondingnon-optimiseddata path +  1,3 4 2 2 2,4 1,3 R3 R2 R6 R5 R4 R1 R2 O1 R5 R4 R1 R3

  17. I1 I1 R3 m2 R5 R2 R1 m4 R4 R3 R1 m3 R4 R2 R5 m1 R5 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 Multiplexers optimised by commutative property +  1,3 4 2 2 2,4 1,3 R3 R2 R6 R5 R4 R1 R2 O1 R5 R4 R1 R3

  18. I1 I1 R3 m2 R5 m4 R4 R2 R1 m3 R5 m1 1,3 2,4 1 2 3 4 1 2,3 4 1,4 2,3 M4 M1 M3 M2 Size of multiplexers reduced +  1,3 4 2 2 2,4 1,3 R3 R2 R6 R5 R4 R1 R2 O1 R5 R4 R1 R3

  19. Design of Controller – stage 1 • All six registers have an enable input, enaRx.ena • M1 and M4 have 1 control input, s:Mx.s • M2 and M3 have 2 control inputs, s1 and s0:Mx.s1 and Mx.s0 • Controller has four states: State1, State2, State3, State4

  20. Design of Controller – details I1 • All six registers have an enable input, enaRx.ena • M1 and M4 have 1 control input, s:Mx.s • M2 and M3 have 2 control inputs, s1 and s0:Mx.s1 and Mx.s0 • Controller has four states: State1, State2, State3, State4 I1 R3 m2 R5 m4 R4 R2 R1 m3 R5 m1 1,3 2,4 1 2 3 4 1 2,3 4 1,4 2,3 M4 M1 M3 M2 +  1,3 4 2 2 2,4 1,3 R3 R2 R6 R5 R4 R1 R2 R4 R1 R3 R5 O1

  21. Design of Controller – stage 2 R1.ena = M1.s = M3.s0 = State2 + State4 R2.ena = R3.ena = State1 + State3 R4.ena = R5.ena = State2 R6.ena = M2.s1 = State4 M2.s0 = M4.s = State2 + State3 M3.s1 = State3 + State4

  22. Controls of muxes Design of Controller – details I1 • R1.ena = M1.s = M3.s0 = State2 + State4 • R2.ena = R3.ena = State1 + State3 • R4.ena = R5.ena = State2 • R6.ena = M2.s1 = State4 • M2.s0 = M4.s = State2 + State3 • M3.s1 = State3 + State4 I1 R3 m2 R5 m4 R4 R2 R1 m3 R5 m1 1,3 2,4 1 2 3 4 1 2,3 4 1,4 2,3 M4 M1 M3 M2 +  1,3 4 2 2 2,4 1,3 R3 R2 R6 R5 R4 R1 R2 O1 R5 R4 R1 R3

  23. Design of Controller – stage 2 R1.ena = M1.s = M3.s0 = State2 + State4 R2.ena = R3.ena = State1 + State3 R4.ena = R5.ena = State2 R6.ena = M2.s1 = State4 M2.s0 = M4.s = State2 + State3 M3.s1 = State3 + State4

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