Worst-case Delay Analysis Considering the Variability of Transistors and Interconnects

1. Worst-case Delay Analysis Considering the Variability of Transistors and Interconnects Takayuki Fukuoka, Tsuchiya Akira and Hidetoshi Onodera Kyoto University

2. Outline • Motivation • Worst-delay Analysis • Classification of the Worst-delay Direction • Conclusions

3. Motivation • Technology scaling • Increasing significance of variation • Transistor and Interconnect variations affect delay variation • Gate length, width etc. • Metal width, ILD (inter layer dielectric) etc. • Worst-delay corner depends on many parameters (Drive strength, Interconnect length etc.) Where is the worst-delay corner? How the corner changes?

4. Outline • Motivation • Worst-delay Analysis • Interconnect Model • Delay Model • Worst-delay Corner • Case Study • Classification of the Worst-delay Direction • Conclusions

5. Interconnect Model • Interconnect structure variation (W, T and H) • Pitch (S+W) is constant • R, C and RC variations • Not statistically independent of R and C variations • As R increases, C decreases Cross section model for interconnects

6. R max RC max R max RC max R variation[%] R variation[%] C max C max C variation[%] C variation[%] R and C variations ITRS2005 80nm Intermediate W, T, H 3σ=20% • C max • Interconnect becomes thick • (W+, T+, H-) • R and RC max • Interconnect becomes thin • (W-, T-, H-) S=W S=3W • Wider Spacing • C variation decreases • R variation does not change Opposite direction

7. Delay Model Delay formula of a RC distributed line [S.Sakurai, IEEE trans. ’93] • Transistor variation Rtr variation • Interconnect variation W, T, H variations Every part of the interconnect is uniformly fluctuated

8. Delay Variation Model • Delay is linear combination of parameters • W, T, H and Rtr are normally distributed • Delay is normally distributed • Statistical worst-delay is : nominal value : standard deviation

9. Worse-delay Corner Normalization relative values of sensitivity coefficients Worst-delay corner ( ) thickness width (W-14%, T-14%)

10. Case Study • ITRS2005 80nm • High performance model: • Intermediate Interconnect: • W, T, H and Rtr variations: • Realistic Drive strength and Interconnect length • Optimally-buffered interconnect length: 94um • Optimal drive strength: 32X buffer Optimum length

11. Experimental Results(drive strength) thickness Drive strength: 1X Drive strength: 32X 7% -2% 10% width Opposite direction -8%

12. Experimental Results (Spacing) Spacing: S=W Drive strength: 1X Spacing: S=3W Drive strength: 1X Wider spacing W and T effects (C effect) become small Worst-delay corner depends on many parameters (drive strength, spacing, etc.)

13. Outline • Motivation • Worst-delay Analysis • Classification of the Worst-delay Direction • Conclusions

14. Idea of Classification • Worst-delay Direction • Interconnect becomes thick (W+, T+) or thin (W-, T-) • Dominant factor • C: interconnect thick delay increases • R, RC: interconnect thin delay increases We compare the proportion of each term The largest term is the dominant factor

15. 1 1 2 2 3 3 4 4 Example of C-dominant case RC dominant Drive strength:１X Spacing: S=W C dominant • C dominant • Second term (RtrC) > Forth term (RCL) • Drive strength is small. • As interconnect becomes thick (C increases), delay increases. • Rtr also affects delay • RC dominant • Long interconnect • As Interconnect becomes thin (R increases), delay increases.

16. 1 1 2 2 3 3 4 4 Example of R-and RC-dominant case Drive strength:32X Spacing: S=W RC dominant R dominant large drive strength Rtr decreases and CL increases (RtrC decreases and RCL increases) As interconnect becomes thin, delay increases. Optimum drive strength

17. Intermediate vs. Global Intermediate (thin) Global (thick) The boundary of each dominant region changes depending on layer R and RC dominant regions become smaller. Global: R is small

18. Minimum Spacing vs. Wider Spacing Spacing: S=W Spacing: S=3W C variation becomes smaller. C dominant regions become smaller. Wider spacing

19. Conclusions • We propose a criterion for classifying the worst-delay direction • Worst-delay corner is context-dependent • Small drive strength: Thicker interconnect worst-delay • Large drive strength or long interconnect: Thinner interconnect worst-delay • This criterion is used as a guideline for the selection of interconnect parasitic values used for the worst-delay calculation.